Fix dhrystone timing code
[riscv-tests.git] / isa /
2015-04-13 Andrew WatermanMerge pull request #3 from joerchan/master
2015-04-13 Joakim AnderssonCorrect expected high value of multiplication
2015-04-12 Joakim AnderssonBetter coverage of mul high instructions
2015-04-04 Andrew WatermanRun RV32 tests on spike with --isa=RV32
2015-03-27 Andrew WatermanNew virtual memory implementation (Sv39)
2015-03-25 Yunsup Leesplit out S-mode tests and M-mode tests
2015-03-25 Andrew WatermanDon't assume PRV1/2 and IE1/2 are reset
2015-03-21 Andrew WatermanMerge rv64si and rv32si tests
2015-03-21 Andrew WatermanAdd fdiv test
2015-03-17 Yunsup Leerelay hwacha cause/aux to scause/sbadaddr
2015-03-17 Andrew WatermanMerge [shm]call into ecall, [shm]ret into eret
2015-03-16 Yunsup Leerevamp vector tests with new privileged spec, and add...
2015-03-14 Andrew WatermanAdd PTE dirty bit test
2015-03-13 Andrew WatermanUpdate to new privileged spec
2015-02-24 Christopher CelioAdded more +/- NaN/inf tests for fcvt.{w/l/wu/lu}....
2015-02-23 Christopher CelioAdded -NaN test for fcvt.{w/h}.s
2015-02-19 Andrew WatermanUnify rv32/rv64 timer tests
2015-02-16 Andrew WatermanMake rv64uf-p-ldst test the sign bit, too
2015-01-10 Andrew WatermanAdd LICENSE
2015-01-05 Andrew WatermanAvoid deprecated "b" pseudo-op; use "j" instead
2015-01-03 Andrew WatermanOn misaligned fetch, EPC = branch target, not source
2014-12-04 Andrew WatermanUse new toolchain and calling convention
2014-12-04 Andrew WatermanRely on assembler to relax far branches
2014-12-04 Andrew WatermanMake timer test more thorough
2014-11-22 Yunsup Leerelax rv32si timer test a bit
2014-11-13 Yunsup Leeremove zscale specific tests
2014-11-13 Yunsup Leeenable make subsets
2014-11-13 Yunsup Leemake rv32si fault load/store test stronger
2014-11-13 Yunsup Leebeef up rv32si tests
2014-11-07 Andrew WatermanFix build with riscv-gcc version 4.9
2014-11-07 Andrew WatermanDon't access memory outside of the binary's range
2014-08-28 Christopher CelioAdded "simple" test to rv32ui.
2014-05-08 Andrew WatermanAdd timer interrupt test
2014-04-18 Christopher CelioAdded a new test case to REMW.
2014-04-09 Stephen TwiggAdjust hwacha misaligned instruction test to ignore...
2014-03-18 Andrew WatermanCheck FP corner cases and flags
2014-03-07 Andrew WatermanAdd fclass.{s|d} test
2014-03-02 Yunsup Leeadd vfmsv.{s,d} tests
2014-02-28 Yunsup Leeadd keepcfg test
2014-02-27 Yunsup Leetest to see whether vector unit is able to take 2 fmas...
2014-02-11 Adam IzraelevitzMerge branch 'master' of github.com:ucb-bar/riscv-tests
2014-02-11 Andrew WatermanRevert to old AUIPC definition
2014-02-04 Quan NguyenAdd vfmsv instruction test, change vsetprec to vsetucfg
2014-02-01 Andrew WatermanShrink hex dumps
2014-02-01 Andrew WatermanAdd rv32si tests, including illegality of shamt[5]
2014-01-31 Andrew WatermanMake CSR test much more robust
2014-01-31 Andrew WatermanReference TESTNUM instead of x28 directly
2014-01-24 Eric LoveDone with rv32ui asm test ports
2014-01-24 Eric LoveFixed srl, srli
2014-01-24 Eric Lovesrl and srai
2014-01-23 Eric LoveFirst round of rv32ui asm tests
2014-01-22 Andrew WatermanAdd CSRRx/CSRRxI test
2014-01-21 Quan NguyenAdd packed vvadd test for confprec Hwacha
2014-01-16 Andrew WatermanMake LR/SC test more thorough
2013-11-29 Albert OuFix load offsets for the vvadd_fw test
2013-11-24 Andrew WatermanUpdate to new privileged ISA
2013-11-20 Quan NguyenAdd rv64uv-p-amoxor_{w,d} tests
2013-11-20 Yunsup Leefix rv64uv/vvadd_fd test to correctly check results
2013-11-06 Yunsup Leecorrectly set SR_EA bit for all vector physical supervi...
2013-11-06 Yunsup Leecorrectly set SR_EA bit for all vector physical tests
2013-10-19 Yunsup Leerevamp pt tests as well
2013-10-19 Yunsup Leehwacha virtual tests working
2013-10-18 Yunsup Leeadd hwacha exception support
2013-10-17 Yunsup Leedisable vector bank tests
2013-10-17 Yunsup Leeadd passing physical vector tests back in
2013-10-17 Yunsup Leeupdate out-of-date floating-point test in rv64uv
2013-10-17 Yunsup Leefix broken amoor_w rv64uv test
2013-10-10 Christopher CelioMerge branch 'master' of github.com:ucb-bar/riscv-tests
2013-10-10 Yunsup Leerevamp hwacha tests
2013-09-21 Andrew WatermanRe-enable virtual memory tests
2013-09-21 Andrew WatermanNew AUIPC semantics
2013-09-11 Andrew WatermanAdd AMOXOR test
2013-08-25 Andrew Watermandon't emit vvcfg for now
2013-08-24 Andrew WatermanReflect changes to ISA
2013-08-24 Sebastien MiroloMerge pull request #1 from smirolo/configure
2013-08-12 Sebastien MiroloMerge branch 'master' of git://github.com/ucb-bar/riscv...
2013-07-26 Andrew WatermanRemove JALR static hints
2013-07-24 Sebastien Mirolofeature: add autoconf
2013-06-10 Andrew WatermanDon't disassemble zeros
2013-05-16 Yunsup Leeadd failing multiply test
2013-05-14 Yunsup Leechange riscv-isa-run to spike
2013-05-02 Andrew Watermanuse RVTEST_RV64UF macro for FPU tests
2013-04-30 Andrew Watermanadd first RV32 tests
2013-04-24 Yunsup Leeadd gitignore
2013-04-24 Yunsup Leecleanup Makefiles in isa
2013-04-24 Yunsup Leeadd missing RVTEST_CODE_END macros
2013-04-24 Yunsup Leeadd more header information to test_macros
2013-04-22 Yunsup Leeinitial commit