riscv-tests.git
3 years agoVerify that mtval/stval is written correctly on misaligned fetch
Andrew Waterman [Wed, 20 Sep 2017 17:47:11 +0000 (10:47 -0700)]
Verify that mtval/stval is written correctly on misaligned fetch

3 years agoFix rv64mi-csr for the case where U-mode is not available. (#86)
Richard Xia [Fri, 27 Oct 2017 04:33:49 +0000 (21:33 -0700)]
Fix rv64mi-csr for the case where U-mode is not available. (#86)

3 years agoIncrease dual-core RV64 timeouts.
Tim Newsome [Tue, 24 Oct 2017 18:55:01 +0000 (11:55 -0700)]
Increase dual-core RV64 timeouts.

I need this for CompareSections to pass when I instrument spike to be
really slow.

3 years agoGet helpful gdb output in MemTestBlock.
Tim Newsome [Thu, 19 Oct 2017 20:21:26 +0000 (13:21 -0700)]
Get helpful gdb output in MemTestBlock.

3 years agoPay attention to server_timeout_sec
Tim Newsome [Thu, 12 Oct 2017 18:53:22 +0000 (11:53 -0700)]
Pay attention to server_timeout_sec

Fixes #83.

3 years agoResurrect priv tests.
Tim Newsome [Sat, 30 Sep 2017 21:48:15 +0000 (14:48 -0700)]
Resurrect priv tests.

3 years agoMerge pull request #79 from riscv/multigdb
Tim Newsome [Wed, 4 Oct 2017 19:40:30 +0000 (12:40 -0700)]
Merge pull request #79 from riscv/multigdb

Multigdb support

3 years agoMake ExamineTarget multi-core aware.
Tim Newsome [Fri, 29 Sep 2017 22:41:30 +0000 (15:41 -0700)]
Make ExamineTarget multi-core aware.

Now on multi-core targets it only runs once, wasting less time.

3 years agoFix tests to work in multi-gdb mode.
Tim Newsome [Fri, 29 Sep 2017 20:20:30 +0000 (13:20 -0700)]
Fix tests to work in multi-gdb mode.

The Gdb class now can handle connecting to more than one gdb. It
enumerates the harts across all connections, and when asked to select a
hart, it transparently sends future gdb commands to the correct
instance.

Multicore tests still have to be aware of some differences. The main one
is that when executing 'c' in RTOS mode, all harts resume, while in
multi-gdb mode only the current one resumes. Additionally, gdb doesn't
set breakpoints until 'c' is issued, so the hart where breakpoints are
set needs to be resumed before other harts might see them.

3 years agoRemove unused function.
Tim Newsome [Fri, 22 Sep 2017 19:57:51 +0000 (12:57 -0700)]
Remove unused function.

3 years agoAdd coverage for single-core non-rtos OpenOCD.
Tim Newsome [Thu, 21 Sep 2017 22:19:47 +0000 (15:19 -0700)]
Add coverage for single-core non-rtos OpenOCD.

3 years agoAllow multiple reset vectors.
Tim Newsome [Wed, 20 Sep 2017 00:10:36 +0000 (17:10 -0700)]
Allow multiple reset vectors.

Some boards have jumpers that control the reset vector, and forcing them
one way or another is more annoying than dealing with it in software.

3 years agoLink against libm for fma()
Andrew Waterman [Tue, 19 Sep 2017 21:34:42 +0000 (14:34 -0700)]
Link against libm for fma()

3 years agoMerge pull request #76 from riscv/multicore
Tim Newsome [Tue, 19 Sep 2017 21:12:12 +0000 (14:12 -0700)]
Merge pull request #76 from riscv/multicore

Add interrupts to MulticoreRunHaltStepiTest.

3 years agoForgot to commit this earlier.
Tim Newsome [Tue, 19 Sep 2017 18:23:35 +0000 (11:23 -0700)]
Forgot to commit this earlier.

Fixes #77.

3 years agoAdd interrupts to MulticoreRunHaltStepiTest.
Tim Newsome [Mon, 18 Sep 2017 18:31:08 +0000 (11:31 -0700)]
Add interrupts to MulticoreRunHaltStepiTest.

Just to hammer on anything at once, and hopefully catch weird
interactions if they exist.

3 years agoDon't read entire log into RAM just to print it.
Tim Newsome [Fri, 15 Sep 2017 19:03:52 +0000 (12:03 -0700)]
Don't read entire log into RAM just to print it.

3 years agomisa is stored in the hart now, not the target
Tim Newsome [Thu, 14 Sep 2017 23:26:51 +0000 (16:26 -0700)]
misa is stored in the hart now, not the target

3 years agoWhen spike fails to launch, display its output.
Tim Newsome [Thu, 14 Sep 2017 19:59:08 +0000 (12:59 -0700)]
When spike fails to launch, display its output.

3 years agoTest debugging code with interrupts.
Tim Newsome [Wed, 13 Sep 2017 01:48:44 +0000 (18:48 -0700)]
Test debugging code with interrupts.

3 years agoCall postMortem() when a test fails.
Tim Newsome [Tue, 12 Sep 2017 18:21:06 +0000 (11:21 -0700)]
Call postMortem() when a test fails.

3 years agoClarify timeout units.
Tim Newsome [Tue, 12 Sep 2017 18:20:27 +0000 (11:20 -0700)]
Clarify timeout units.

3 years agoMove link options to end of gcc command line
Andrew Waterman [Thu, 14 Sep 2017 18:11:44 +0000 (11:11 -0700)]
Move link options to end of gcc command line

3 years agoMerge pull request #69 from riscv/multicore
Tim Newsome [Tue, 12 Sep 2017 16:36:34 +0000 (09:36 -0700)]
Merge pull request #69 from riscv/multicore

Proper multicore support for debug tests

3 years agoImprove ma_fetch test to cover JAL and branches
Andrew Waterman [Fri, 1 Sep 2017 18:15:44 +0000 (11:15 -0700)]
Improve ma_fetch test to cover JAL and branches

3 years agoAdd some infrastructure for multicore tests.
Tim Newsome [Fri, 1 Sep 2017 19:31:15 +0000 (12:31 -0700)]
Add some infrastructure for multicore tests.

When compiling, define the number of harts. This means we only need to
allocate a lot of stack if there are a lot of harts.

3 years agoUse 32-bit link script for 32-bit target.
Tim Newsome [Fri, 1 Sep 2017 19:03:40 +0000 (12:03 -0700)]
Use 32-bit link script for 32-bit target.

3 years agoThis file isn't ready yet.
Tim Newsome [Mon, 28 Aug 2017 20:40:15 +0000 (13:40 -0700)]
This file isn't ready yet.

3 years agoForgot to add this file.
Tim Newsome [Mon, 28 Aug 2017 19:43:08 +0000 (12:43 -0700)]
Forgot to add this file.

3 years agoIncrease remotetimeout for spike targets.
Tim Newsome [Mon, 28 Aug 2017 19:17:37 +0000 (12:17 -0700)]
Increase remotetimeout for spike targets.

On overloaded systems, when executing compare-sections, otherwise gdb
might hit a timeout and the compare-sections code doesn't deal with it.
(You get an error message complaining that 130 is not a valid hex
digit.)

3 years agoFix rebase bug.
Tim Newsome [Tue, 15 Aug 2017 22:32:24 +0000 (15:32 -0700)]
Fix rebase bug.

3 years agoMake MemTestBlock output a more descriptive error.
Tim Newsome [Sun, 13 Aug 2017 20:56:44 +0000 (13:56 -0700)]
Make MemTestBlock output a more descriptive error.

3 years agoFix MemTest* after sloppy rebase.
Tim Newsome [Sun, 13 Aug 2017 19:50:39 +0000 (12:50 -0700)]
Fix MemTest* after sloppy rebase.

3 years agoRename test to MulticoreRunHaltStepiTest.
Tim Newsome [Fri, 11 Aug 2017 20:25:06 +0000 (13:25 -0700)]
Rename test to MulticoreRunHaltStepiTest.

3 years agoMake pylint happy.
Tim Newsome [Fri, 11 Aug 2017 19:55:25 +0000 (12:55 -0700)]
Make pylint happy.

3 years agoWIP multicore testing.
Tim Newsome [Thu, 10 Aug 2017 18:27:04 +0000 (11:27 -0700)]
WIP multicore testing.

3 years agoWIP towards multiple gdb instances.
Tim Newsome [Mon, 7 Aug 2017 22:13:09 +0000 (15:13 -0700)]
WIP towards multiple gdb instances.

3 years agoMake the debug tests aware of multicore.
Tim Newsome [Mon, 7 Aug 2017 19:51:42 +0000 (12:51 -0700)]
Make the debug tests aware of multicore.

Targets now contain an array of harts. When running a regular test, one
hart is selected to run the test on while the remaining harts are parked
in a safe infinite loop.

There's currently only one test that tests multicore behavior, but there
could be more.

The infrastructure should be able to support heterogeneous multicore,
but I don't have a target like that to test with.

3 years agoIncrease delay in UserInterrupt.
Tim Newsome [Mon, 28 Aug 2017 19:11:49 +0000 (12:11 -0700)]
Increase delay in UserInterrupt.

When a machine is very loaded, otherwise it could happen that we send
the interrupt before the resume has actually happened.

3 years agoMerge pull request #67 from riscv/sfence_vma
Palmer Dabbelt [Wed, 16 Aug 2017 20:42:50 +0000 (13:42 -0700)]
Merge pull request #67 from riscv/sfence_vma

Inform GCC that "sfence.vma" clobbers memory

3 years agoInform GCC that "sfence.vma" clobbers memory
Palmer Dabbelt [Wed, 16 Aug 2017 19:26:25 +0000 (12:26 -0700)]
Inform GCC that "sfence.vma" clobbers memory

3 years agoPut logfile code back so everything works again.
Tim Newsome [Mon, 14 Aug 2017 22:24:41 +0000 (15:24 -0700)]
Put logfile code back so everything works again.

I don't exactly understand why it has to be the way it is, but I just
want it to work.

Also fix a pylint complaint.

3 years agoMerge pull request #66 from riscv/debug_user_niceness
Megan Wachs [Mon, 14 Aug 2017 20:33:31 +0000 (13:33 -0700)]
Merge pull request #66 from riscv/debug_user_niceness

Debug: Usability Features

3 years agodebug: clean up Temporary Log File messages
Megan Wachs [Mon, 14 Aug 2017 20:26:02 +0000 (13:26 -0700)]
debug: clean up Temporary Log File messages

3 years agodebug: Avoid None type error
Megan Wachs [Mon, 14 Aug 2017 20:24:04 +0000 (13:24 -0700)]
debug: Avoid None type error

3 years agodebug: Revert change to print backtrace, as that is actually already printed
Megan Wachs [Mon, 14 Aug 2017 17:59:34 +0000 (10:59 -0700)]
debug: Revert change to print backtrace, as that is actually already printed

3 years agodebug: Allow OpenOCD startup timeout to be specified. Print out path to log files.
Megan Wachs [Mon, 14 Aug 2017 17:58:22 +0000 (10:58 -0700)]
debug: Allow OpenOCD startup timeout to be specified. Print out path to log files.

3 years agoWhen a test fails with exception, actually print out the reason why.
Megan Wachs [Mon, 14 Aug 2017 17:17:01 +0000 (10:17 -0700)]
When a test fails with exception, actually print out the reason why.

3 years agoMake MemTest* catch reading too many words.
Tim Newsome [Sun, 13 Aug 2017 19:33:07 +0000 (12:33 -0700)]
Make MemTest* catch reading too many words.

For one of the test addresses, use the highest possible one to ensure
that OpenOCD isn't secretly reading/writing more words than requested.

3 years agoShow the OpenOCD log in all(?) failure cases.
Tim Newsome [Fri, 11 Aug 2017 21:56:36 +0000 (14:56 -0700)]
Show the OpenOCD log in all(?) failure cases.

3 years agoPrint out name of logfile when debug test is run.
Tim Newsome [Fri, 11 Aug 2017 21:33:54 +0000 (14:33 -0700)]
Print out name of logfile when debug test is run.

3 years agoWhen make fails to run a test, print out the log.
Tim Newsome [Fri, 11 Aug 2017 21:13:41 +0000 (14:13 -0700)]
When make fails to run a test, print out the log.

3 years agoDon't use `set pipefail` which is a bashism.
Tim Newsome [Fri, 11 Aug 2017 18:15:11 +0000 (11:15 -0700)]
Don't use `set pipefail` which is a bashism.

Instead, just give up on making the log files altogether now. Since
gdbserver.py makes its own log files it's not as necessary in any case.

This is yet another commit in an attempt to get the riscv-tools build to
actually fail if these tests fail.

3 years agoDon't eat errors in debug Makefile.
Tim Newsome [Fri, 11 Aug 2017 17:48:19 +0000 (10:48 -0700)]
Don't eat errors in debug Makefile.

3 years agoDon't run debug tests as part of build.
Tim Newsome [Thu, 10 Aug 2017 21:23:29 +0000 (14:23 -0700)]
Don't run debug tests as part of build.

Testing is a separate step.

Also fix Issue #64 by adding src_dir to the path to the targets file.

3 years agoPylint target files as well.
Tim Newsome [Thu, 10 Aug 2017 20:30:37 +0000 (13:30 -0700)]
Pylint target files as well.

This would have prevented some bugs I committed earlier.

3 years agoGive these sim targets a chance of passing.
Tim Newsome [Thu, 10 Aug 2017 18:43:49 +0000 (11:43 -0700)]
Give these sim targets a chance of passing.

Also make sure vsim.log makes it into the generated log file.

3 years agoMerge pull request #62 from richardxia/only-emit-f-instructions-when-compiled-for-f
Palmer Dabbelt [Tue, 8 Aug 2017 22:37:26 +0000 (15:37 -0700)]
Merge pull request #62 from richardxia/only-emit-f-instructions-when-compiled-for-f

rv64[ms]i-csr: Only emit F instructions when compiled for F.

3 years agorv64[ms]i-csr: Only emit F instructions when compiled for F.
Richard Xia [Mon, 7 Aug 2017 23:57:14 +0000 (16:57 -0700)]
rv64[ms]i-csr: Only emit F instructions when compiled for F.

3 years agoRV32 div tests should use -2^31 for min value, not -2^63
Andrew Waterman [Fri, 4 Aug 2017 17:20:00 +0000 (10:20 -0700)]
RV32 div tests should use -2^31 for min value, not -2^63

3 years agoImprove RVC test
Andrew Waterman [Fri, 4 Aug 2017 07:23:04 +0000 (00:23 -0700)]
Improve RVC test

Make the page-crossing instruction non-idempotent to detect erroneously
executing the first 16 bits of the instruction with garbage MSBs.

4 years agoFix the end of MulticoreTest.
Tim Newsome [Mon, 31 Jul 2017 20:49:34 +0000 (13:49 -0700)]
Fix the end of MulticoreTest.

Now it actually confirms that we're talking to two different cores which
have different values in their registers. Previously it could have been
fooled if eg. the thread command was a nop.

4 years agoMake pylint happy.
Tim Newsome [Thu, 27 Jul 2017 20:34:54 +0000 (13:34 -0700)]
Make pylint happy.

4 years agoUse new OpenOCD messages to determine gdb port.
Tim Newsome [Wed, 26 Jul 2017 14:56:35 +0000 (07:56 -0700)]
Use new OpenOCD messages to determine gdb port.

This is simpler and more reliable than playing around with lsof.
Specifically, it works if the OpenOCD command is "strace openocd" while
the previous code did not.

4 years agoOnly clean up logfiles that we know we created.
Tim Newsome [Fri, 21 Jul 2017 18:49:15 +0000 (11:49 -0700)]
Only clean up logfiles that we know we created.

4 years agoAdd back code to clean up triggers in entry.S
Tim Newsome [Fri, 21 Jul 2017 03:43:18 +0000 (20:43 -0700)]
Add back code to clean up triggers in entry.S

Then for targets that can't handle this because they don't implement
hmode, add a target setting that allows that to be specified.

4 years agoCheck all PCs after reset.
Tim Newsome [Tue, 18 Jul 2017 18:35:59 +0000 (11:35 -0700)]
Check all PCs after reset.

4 years agoPrint out logs in more failure cases.
Tim Newsome [Thu, 13 Jul 2017 03:26:21 +0000 (20:26 -0700)]
Print out logs in more failure cases.

4 years agoMerge pull request #58 from riscv/fpga_reset_halt
Tim Newsome [Thu, 6 Jul 2017 22:09:09 +0000 (15:09 -0700)]
Merge pull request #58 from riscv/fpga_reset_halt

debug: Make the 'out of reset' tests apply reset

4 years agodebug: Make the 'out of reset' tests actually apply reset
mwachs5 [Thu, 6 Jul 2017 22:04:27 +0000 (15:04 -0700)]
debug: Make the 'out of reset' tests actually apply reset

4 years agoAdd gdb_setup to target for arbitrary gdb commands
Tim Newsome [Mon, 3 Jul 2017 17:48:58 +0000 (10:48 -0700)]
Add gdb_setup to target for arbitrary gdb commands

I'm using this for a target where misa is at an old address, to
set riscv use_compressed_breakpoints off

4 years agoDon't clear triggers during execution.
Tim Newsome [Mon, 3 Jul 2017 17:36:03 +0000 (10:36 -0700)]
Don't clear triggers during execution.

This shouldn't affect triggers set by the debugger, because running code
can't change those. When it does affect them, it breaks Hwbp1 which sets
the breakpoint before running the program.

4 years agoTolerate missing misa register.
Tim Newsome [Tue, 27 Jun 2017 17:53:16 +0000 (10:53 -0700)]
Tolerate missing misa register.

At least in the test programs. There are other places where this causes
trouble as well.

4 years agoMerge pull request #55 from riscv/debug
Tim Newsome [Tue, 27 Jun 2017 17:28:10 +0000 (10:28 -0700)]
Merge pull request #55 from riscv/debug

Test gdb/OpenOCD during regular test run.

4 years agoMerge pull request #56 from riscv/config
Tim Newsome [Tue, 27 Jun 2017 17:27:41 +0000 (10:27 -0700)]
Merge pull request #56 from riscv/config

Move target definition into individual files.

4 years agoMove target definition into individual files.
Tim Newsome [Mon, 26 Jun 2017 17:00:34 +0000 (10:00 -0700)]
Move target definition into individual files.

Instead of defining each target in targets.py, now each target gets its
own .py file. This means people can easily keep their own target files
around that they may not want to put into the main test source. As part
of that, I removed the freedom-u500-sim target since I assume it's only
used internally at SiFive.

Added a few cleanups as well:
* Update README examples, mostly --sim_cmd instead of --cmd.
* Allow defining misa in a target, to skip running of ExamineTarget.
* Rename target.target() to target.create(), which is less confusing.
* Default --sim_cmd to `spike`
* Got rid of `use_fpu`, instead looking at F or D in $misa.

4 years agoTest gdb/OpenOCD during regular test run.
Tim Newsome [Fri, 23 Jun 2017 19:15:25 +0000 (12:15 -0700)]
Test gdb/OpenOCD during regular test run.

4 years agoAdd basic multicore test.
Tim Newsome [Fri, 23 Jun 2017 01:37:55 +0000 (18:37 -0700)]
Add basic multicore test.

4 years agoSmoketest multicore.
Tim Newsome [Tue, 20 Jun 2017 22:02:28 +0000 (15:02 -0700)]
Smoketest multicore.

When connecting to gdb, select a random thread and use that for the
current test.

Also replace infinite_loop with something that will later allow
smoketesting of more than one thread.

4 years agoWrite OpenOCD log when it crashes early.
Tim Newsome [Mon, 19 Jun 2017 16:13:51 +0000 (09:13 -0700)]
Write OpenOCD log when it crashes early.

4 years agoStore logs for all tests in logs/
Tim Newsome [Fri, 16 Jun 2017 18:30:46 +0000 (11:30 -0700)]
Store logs for all tests in logs/

This creates a record of passing as well as failing tests, and gets rid
of the log clutter that you previously ended up with in the current
directory.

4 years agoTest 64-bit addressing.
Tim Newsome [Thu, 15 Jun 2017 19:58:40 +0000 (12:58 -0700)]
Test 64-bit addressing.

The spike64 target now links all test programs at 0x7fff_ffff_ffff_0000.

Also a minor change to log file naming so that 'make all' works again.
I'll fix this better later.

4 years agoAdd final echo to E300/U500 OpenOCD scripts
Tim Newsome [Fri, 9 Jun 2017 23:54:22 +0000 (16:54 -0700)]
Add final echo to E300/U500 OpenOCD scripts

4 years agoMake HiFive1 testing (mostly) work again
Tim Newsome [Fri, 9 Jun 2017 21:09:35 +0000 (14:09 -0700)]
Make HiFive1 testing (mostly) work again

Currently failing:
    DebugChangeString
    DebugFunctionCall
    InstantHaltTest

4 years agoFix using defaults for --server_cmd and --sim_cmd
Tim Newsome [Fri, 9 Jun 2017 21:08:42 +0000 (14:08 -0700)]
Fix using defaults for --server_cmd and --sim_cmd

4 years agoDefault to openocd, not riscv-openocd
Tim Newsome [Fri, 9 Jun 2017 17:59:43 +0000 (10:59 -0700)]
Default to openocd, not riscv-openocd

AFAICT the normal build process never builds a binary called
riscv-openocd.

4 years agoMake pylint happy.
Tim Newsome [Mon, 5 Jun 2017 18:46:39 +0000 (11:46 -0700)]
Make pylint happy.

If we want we can start using print(), but if so let's consistently use
it instead of piecemeal. See also
https://stackoverflow.com/questions/28694380/pylint-says-unnecessary-parens-after-r-keyword

4 years agoMerge pull request #53 from richardxia/fail-if-simulator-exits-early
Palmer Dabbelt [Thu, 25 May 2017 19:14:06 +0000 (12:14 -0700)]
Merge pull request #53 from richardxia/fail-if-simulator-exits-early

Fail if simulator exits early.

4 years agoFail if simulator exits early.
Richard Xia [Tue, 23 May 2017 20:38:08 +0000 (13:38 -0700)]
Fail if simulator exits early.

4 years agominNum -> minimumNumber
Andrew Waterman [Mon, 22 May 2017 20:40:52 +0000 (13:40 -0700)]
minNum -> minimumNumber

4 years agoMerge pull request #52 from riscv/vcs_sim_cmd
Megan Wachs [Thu, 18 May 2017 19:14:07 +0000 (12:14 -0700)]
Merge pull request #52 from riscv/vcs_sim_cmd

debug: Correct the calling for a 32-bit simulation target

4 years agodebug: Correct the calling for a 32-bit simulation target
Megan Wachs [Thu, 18 May 2017 19:09:40 +0000 (12:09 -0700)]
debug: Correct the calling for a 32-bit simulation target

4 years agoManually assemble bad shift amount, since assembler rejects
Andrew Waterman [Wed, 17 May 2017 22:26:27 +0000 (15:26 -0700)]
Manually assemble bad shift amount, since assembler rejects

Resolves #51

4 years agoShorten the debug tests
Palmer Dabbelt [Wed, 17 May 2017 17:50:55 +0000 (10:50 -0700)]
Shorten the debug tests

4 years agoMerge pull request #49 from riscv/no_examine_target
Palmer Dabbelt [Wed, 17 May 2017 17:50:28 +0000 (10:50 -0700)]
Merge pull request #49 from riscv/no_examine_target

No Examine Target

4 years agoShow the debug logs to stdout, to avoid travis timeouts
Palmer Dabbelt [Wed, 17 May 2017 15:28:16 +0000 (08:28 -0700)]
Show the debug logs to stdout, to avoid travis timeouts

4 years agodebug: remove unused auto_int function
Megan Wachs [Tue, 16 May 2017 21:43:43 +0000 (14:43 -0700)]
debug: remove unused auto_int function

4 years agodebug: Allow skipping the ExamineTarget task.
Megan Wachs [Tue, 16 May 2017 21:40:29 +0000 (14:40 -0700)]
debug: Allow skipping the ExamineTarget task.

4 years agodebug: Allow skipping the ExamineTarget step by specifying misa
Megan Wachs [Tue, 16 May 2017 21:25:39 +0000 (14:25 -0700)]
debug: Allow skipping the ExamineTarget step by specifying misa

4 years agoMerge pull request #47 from riscv/debug-0.13
Palmer Dabbelt [Tue, 16 May 2017 20:48:55 +0000 (13:48 -0700)]
Merge pull request #47 from riscv/debug-0.13

Debug 0.13 Tests