riscv-tests.git
2 years agoAssert if HiFive1 program is too large.
Tim Newsome [Thu, 13 Sep 2018 23:02:22 +0000 (16:02 -0700)]
Assert if HiFive1 program is too large.

2 years agoPut debug test stack in data instead of text
Tim Newsome [Thu, 13 Sep 2018 22:55:17 +0000 (15:55 -0700)]
Put debug test stack in data instead of text

2 years agoMerge branch 'tommythorn-master'
Andrew Waterman [Sat, 8 Sep 2018 22:10:44 +0000 (15:10 -0700)]
Merge branch 'tommythorn-master'

2 years agoRV64 s{ll,ra,rl}w tests with non-canonical values
Tommy Thorn [Sat, 8 Sep 2018 16:00:04 +0000 (09:00 -0700)]
RV64 s{ll,ra,rl}w tests with non-canonical values

2 years agoRevert "breakpoint.S: Don't assume trigger is hardwired to breakpoint (#158) (#159)"
Andrew Waterman [Fri, 7 Sep 2018 01:45:14 +0000 (18:45 -0700)]
Revert "breakpoint.S: Don't assume trigger is hardwired to breakpoint (#158) (#159)"

This reverts commit 901a2694d5384e4ef9af8e4fb0c9a07eb24d0028,
under the advisement of @tommythorn in #158.

2 years agobreakpoint.S: Don't assume trigger is hardwired to breakpoint (#158) (#159)
Tommy Thorn [Thu, 6 Sep 2018 18:07:42 +0000 (11:07 -0700)]
breakpoint.S: Don't assume trigger is hardwired to breakpoint (#158) (#159)

2 years agoMerge pull request #156 from riscv/PrivChange
Tim Newsome [Mon, 3 Sep 2018 22:03:50 +0000 (15:03 -0700)]
Merge pull request #156 from riscv/PrivChange

Reset address translation/perms before PrivChange

2 years agoFix CustomRegisterTest.
Tim Newsome [Fri, 31 Aug 2018 19:53:25 +0000 (12:53 -0700)]
Fix CustomRegisterTest.

gdb in riscv-tools doesn't automatically create a "custom" group like
mainline gdb does.

2 years agoAdd test case for `riscv expose_custom`.
Tim Newsome [Mon, 27 Aug 2018 20:17:51 +0000 (13:17 -0700)]
Add test case for `riscv expose_custom`.

Only works against spike, where I've implemented some custom debug
registers to test against.

2 years agoReset address translation/perms before PrivChange
Tim Newsome [Tue, 28 Aug 2018 20:56:25 +0000 (13:56 -0700)]
Reset address translation/perms before PrivChange

We already did this for PrivTest.

Hopefully solves #155, but I haven't been able to reproduce it.

2 years agoNeuter TriggerStoreAddressInstant
Tim Newsome [Tue, 28 Aug 2018 00:02:37 +0000 (17:02 -0700)]
Neuter TriggerStoreAddressInstant

Now that OpenOCD can tell gdb exactly which watchpoint was hit, this
test exposes another problem:
https://github.com/riscv/riscv-openocd/issues/295

For now neuter the test so the testsuite can still be useful.

2 years agoMake pylint happy.
Tim Newsome [Mon, 27 Aug 2018 20:58:09 +0000 (13:58 -0700)]
Make pylint happy.

2 years agoTemporarily disabling PrivChange test
Andrew Waterman [Sat, 25 Aug 2018 11:33:01 +0000 (04:33 -0700)]
Temporarily disabling PrivChange test

@timsifive we are debugging intermittent failures.

2 years agoMake pylint happy with change d1d2d953b5016b465.
Tim Newsome [Fri, 24 Aug 2018 00:08:18 +0000 (17:08 -0700)]
Make pylint happy with change d1d2d953b5016b465.

2 years agoGet all of the log into the final log file
Tim Newsome [Fri, 24 Aug 2018 00:04:57 +0000 (17:04 -0700)]
Get all of the log into the final log file

This allows me to see the final valgrind output on OpenOCD, so I can
watch for memory leaks when using --server_cmd "valgrind
--leak-check=full openocd".

2 years agoMerge pull request #153 from dmitryryzhov/rtos-switch-active-thread
Tim Newsome [Thu, 23 Aug 2018 23:52:39 +0000 (16:52 -0700)]
Merge pull request #153 from dmitryryzhov/rtos-switch-active-thread

Add debug test, which checks that openocd correctly switch active thread on any hart halt.

2 years agoMerge branch 'master' of https://github.com/riscv/riscv-tests
Tim Newsome [Wed, 22 Aug 2018 20:47:26 +0000 (13:47 -0700)]
Merge branch 'master' of https://github.com/riscv/riscv-tests

2 years agoDisable MulticoreRunHaltStepiTest
Tim Newsome [Wed, 22 Aug 2018 20:46:32 +0000 (13:46 -0700)]
Disable MulticoreRunHaltStepiTest

It's failing (intermittently?). See eg.
https://travis-ci.org/riscv/riscv-tools/builds/418928412?utm_source=github_status&utm_medium=notification

2 years agoAdd debug test, which checks that openocd correctly switch active thread on any hart...
Dmitry Ryzhov [Wed, 22 Aug 2018 15:09:33 +0000 (18:09 +0300)]
Add debug test, which checks that openocd correctly switch active thread on any hart halt.

2 years agoChanging the register mstatus is read into (#152)
Srivatsa Yogendra [Tue, 21 Aug 2018 20:14:07 +0000 (13:14 -0700)]
Changing the register mstatus is read into (#152)

The mstatus reading overwrites the expected user mode cause value.

2 years agoRevert "Fix to solve the failing tests shamt, csr and scall (#151)"
Andrew Waterman [Tue, 21 Aug 2018 02:10:05 +0000 (19:10 -0700)]
Revert "Fix to solve the failing tests shamt, csr and scall (#151)"

This reverts commit 31a91823b7c7becacd06c9c32e44180eea5e4fe7.

These changes should be made to the test environment, not the tests
themselves.

2 years agoFix to solve the failing tests shamt, csr and scall (#151)
Srivatsa Yogendra [Sat, 18 Aug 2018 01:49:16 +0000 (18:49 -0700)]
Fix to solve the failing tests shamt, csr and scall (#151)

* making mtvec_handler global

* Adding the pmp configuration inst

The PMP config instructions are added as the test jumps to user mode

* Adding pmp config inst

Adding pmp config instructions as the test jumps to user mode

* changing to PMP macros

* changing to PMP Macros

* moving the #endif after pmp initialization

* Removing the unwanted label

2 years agomaking mtvec_handler global (#150)
Srivatsa Yogendra [Fri, 17 Aug 2018 19:02:57 +0000 (12:02 -0700)]
making mtvec_handler global (#150)

2 years agoAdd jump/hbreak test.
Tim Newsome [Wed, 8 Aug 2018 21:33:50 +0000 (14:33 -0700)]
Add jump/hbreak test.

2 years agoCheck that SC yields the load reservation
Andrew Waterman [Mon, 9 Jul 2018 21:25:46 +0000 (14:25 -0700)]
Check that SC yields the load reservation

https://github.com/riscv/riscv-isa-manual/commit/03a5e722fc0fe7b94dd0a49f550ff7b41a63f612

2 years agorwatch/watch on explicit address
Tim Newsome [Tue, 3 Jul 2018 20:54:13 +0000 (13:54 -0700)]
rwatch/watch on explicit address

Newer gdb requires more debug info in order to "watch data" in this
test. I'm not sure how to make that debug info happen, so instead we
tell it the address to use.

2 years agoAdd reproduce line to the end of debug test logs
Tim Newsome [Mon, 18 Jun 2018 22:03:05 +0000 (15:03 -0700)]
Add reproduce line to the end of debug test logs

2 years agoMerge pull request #141 from riscv/mrhstest
Tim Newsome [Mon, 21 May 2018 18:56:39 +0000 (11:56 -0700)]
Merge pull request #141 from riscv/mrhstest

Fix MulticoreRunHaltStepiTest

2 years agoFix MulticoreRunHaltStepiTest
Tim Newsome [Sat, 19 May 2018 01:12:00 +0000 (18:12 -0700)]
Fix MulticoreRunHaltStepiTest

The test actually wasn't checking interrupt counts at all. Fixing it
required some other changes:
Make sure all harts get to run
Add some retries, since on a loaded machine against spike both harts
might not get to run, even if you give spike a generous amount of time
to do so.

2 years agoMerge pull request #139 from riscv/debug-tests-more-single
Megan Wachs [Tue, 15 May 2018 17:19:08 +0000 (10:19 -0700)]
Merge pull request #139 from riscv/debug-tests-more-single

Mark more Debug tests as "Single Hart"

2 years agoMerge remote-tracking branch 'origin/downloadtest' into debug-tests-more-single
Megan Wachs [Mon, 14 May 2018 23:04:10 +0000 (16:04 -0700)]
Merge remote-tracking branch 'origin/downloadtest' into debug-tests-more-single

2 years agoMake DownloadTest properly park other harts.
Tim Newsome [Mon, 14 May 2018 22:14:47 +0000 (15:14 -0700)]
Make DownloadTest properly park other harts.

2 years agodebug: remove some unintentionally added newlines
Megan Wachs [Mon, 14 May 2018 21:34:58 +0000 (14:34 -0700)]
debug: remove some unintentionally added newlines

2 years agodebug: Fixing the non-RTOS behavior for DownloadTest
Megan Wachs [Mon, 14 May 2018 15:46:03 +0000 (08:46 -0700)]
debug: Fixing the non-RTOS behavior for DownloadTest

2 years agodebug: mark more tests as single-hart tests
Megan Wachs [Fri, 11 May 2018 16:40:10 +0000 (09:40 -0700)]
debug: mark more tests as single-hart tests

2 years agodebug: output some more useful info into the post-mortem data
Megan Wachs [Fri, 11 May 2018 16:39:48 +0000 (09:39 -0700)]
debug: output some more useful info into the post-mortem data

3 years ago[rv64ua/lrsc] Initialize memory read out. (#135)
Christopher Celio [Tue, 1 May 2018 00:03:50 +0000 (17:03 -0700)]
[rv64ua/lrsc] Initialize memory read out. (#135)

* [rv64ua/lrsc] Initialize memory read out.

Even though the load contents are discarded, this un-initialized memory value
can lead to a divergence for co-simulation between two different RISC-V designs.

* [rv64ua/lrsc] Use .skip instead of .align.

3 years agoFix formatting to make pylint happy.
Tim Newsome [Mon, 30 Apr 2018 19:54:03 +0000 (12:54 -0700)]
Fix formatting to make pylint happy.

3 years agoMerge pull request #132 from riscv/debug-clear-satp
Megan Wachs [Sun, 29 Apr 2018 03:38:37 +0000 (20:38 -0700)]
Merge pull request #132 from riscv/debug-clear-satp

debug: need to clear satp before changing priv

3 years agodebug: need to clear satp before changing priv
Megan Wachs [Fri, 27 Apr 2018 23:52:43 +0000 (16:52 -0700)]
debug: need to clear satp before changing priv

ISA Manual does not require this register to be reset, and attempting to execute code with VM on when VM hasn't been set up is going to just lead to sadness.

3 years agoMerge pull request #125 from riscv/debug-delete-sim
Megan Wachs [Fri, 27 Apr 2018 22:18:57 +0000 (15:18 -0700)]
Merge pull request #125 from riscv/debug-delete-sim

Delete E300Sim.py

3 years agoMerge pull request #130 from riscv/trap_entry_align-1
Megan Wachs [Fri, 27 Apr 2018 22:18:44 +0000 (15:18 -0700)]
Merge pull request #130 from riscv/trap_entry_align-1

debug: add missing align directive on trap_entry

3 years agodebug: add missing align directive on trap_entry
Megan Wachs [Fri, 27 Apr 2018 21:42:34 +0000 (14:42 -0700)]
debug: add missing align directive on trap_entry

3 years agoFix race when making logs directory
Tim Newsome [Tue, 24 Apr 2018 18:21:27 +0000 (11:21 -0700)]
Fix race when making logs directory

3 years agoDelete E300Sim.py
Megan Wachs [Thu, 19 Apr 2018 17:46:23 +0000 (10:46 -0700)]
Delete E300Sim.py

This file is wrong (the .cfg file isn't right) and not used by anything.

3 years agoMerge pull request #123 from riscv/gdb_timeout
Tim Newsome [Mon, 16 Apr 2018 19:14:13 +0000 (12:14 -0700)]
Merge pull request #123 from riscv/gdb_timeout

Compute gdb command timeout based on ops estimate

3 years agoCompute gdb command timeout based on ops estimate
Tim Newsome [Mon, 9 Apr 2018 20:09:55 +0000 (13:09 -0700)]
Compute gdb command timeout based on ops estimate

The caller of gdb.command() should estimate how much work gdb needs to
do, and testlib then scales this up proportional to the general gdb
timeout we configured. This hopefully allows us to configure a tighter
timeout, so we don't have to have a multi-hour timeout just for
something that takes long like `load` on a really slow simulator.

Hopefully this addresses #122.

3 years agoFix #120: Instructions 'sll' are replaced with 'slli' in rv64ui/slli.S (#121)
Andrei Tatarnikov [Mon, 9 Apr 2018 18:24:04 +0000 (21:24 +0300)]
Fix #120: Instructions 'sll' are replaced with 'slli' in rv64ui/slli.S (#121)

3 years agoUse `gdb_report_register_access_error enable`
Tim Newsome [Mon, 2 Apr 2018 21:56:45 +0000 (14:56 -0700)]
Use `gdb_report_register_access_error enable`

3 years agoTest debug authentication.
Tim Newsome [Tue, 27 Feb 2018 22:28:26 +0000 (14:28 -0800)]
Test debug authentication.

Also halt instead of reset spike targets, which tests a more complicated
code path.

3 years agoPrint log filename at the end of the log.
Tim Newsome [Fri, 23 Mar 2018 20:27:52 +0000 (13:27 -0700)]
Print log filename at the end of the log.

This makes it much easier to look at a log if you see a failure
scrolling by on your terminal.

3 years agoMake misa.C test conform to Hauser proposal
Andrew Waterman [Wed, 21 Mar 2018 23:54:08 +0000 (16:54 -0700)]
Make misa.C test conform to Hauser proposal

See https://github.com/riscv/riscv-isa-manual/commit/0472bcdd166f45712492829a250e228bb45fa5e7

3 years agoMerge pull request #119 from rishikhan/master
Palmer Dabbelt [Wed, 21 Mar 2018 01:14:18 +0000 (18:14 -0700)]
Merge pull request #119 from rishikhan/master

Update Makefile to allow for RISCV_PREFIX to be set by the configure

3 years agoUpdate Makefile to allow for RISCV_PREFIX to be set by the configure --target
rishi [Mon, 19 Mar 2018 16:02:53 +0000 (12:02 -0400)]
Update Makefile to allow for RISCV_PREFIX to be set by the configure --target

3 years agoTest debugging with/without a program buffer
Tim Newsome [Mon, 19 Feb 2018 21:31:40 +0000 (13:31 -0800)]
Test debugging with/without a program buffer

3 years agoEnsure an error when reading a non-existent CSR.
Tim Newsome [Thu, 1 Mar 2018 23:05:45 +0000 (15:05 -0800)]
Ensure an error when reading a non-existent CSR.

3 years agoAdd test for clearing misa.C while PC is misaligned (#117)
Andrew Waterman [Tue, 27 Feb 2018 07:25:34 +0000 (01:25 -0600)]
Add test for clearing misa.C while PC is misaligned (#117)

See https://github.com/riscv/riscv-isa-manual/pull/139

3 years agoTest resuming from a trigger.
Tim Newsome [Fri, 9 Feb 2018 16:54:59 +0000 (08:54 -0800)]
Test resuming from a trigger.

3 years agoLink scripts shouldn't be executable.
Tim Newsome [Wed, 7 Feb 2018 21:48:54 +0000 (13:48 -0800)]
Link scripts shouldn't be executable.

3 years agoDeal with gdb reporting pmpcfg0 not existing.
Tim Newsome [Mon, 8 Jan 2018 20:36:49 +0000 (12:36 -0800)]
Deal with gdb reporting pmpcfg0 not existing.

It's an optional register.

3 years agoAdd test for multicore failure
Tim Newsome [Fri, 5 Jan 2018 22:25:57 +0000 (14:25 -0800)]
Add test for multicore failure

Specifically, make sure that after resuming all cores, and halting core
0, that OpenOCD's poll() doesn't mess up the currently selected hart to
the point where memory accesses intended for core 0 go to core 1.

3 years agoTest access exception behavior for illegal addresses (#111)
Andrew Waterman [Wed, 3 Jan 2018 05:13:38 +0000 (21:13 -0800)]
Test access exception behavior for illegal addresses (#111)

OK'd by @palmer-dabbelt

3 years agoTest FPRs that aren't XLEN in size.
Tim Newsome [Wed, 27 Dec 2017 23:41:45 +0000 (15:41 -0800)]
Test FPRs that aren't XLEN in size.

Cover all combinations of 32,64 bit XLEN with F and FD extensions.

Finishes Issue https://github.com/riscv/riscv-openocd/issues/110

3 years agoAdd all-tests target.
Tim Newsome [Fri, 22 Dec 2017 00:00:01 +0000 (16:00 -0800)]
Add all-tests target.

I hope to use this in riscv-tools' regression.sh.

3 years agoMerge pull request #110 from riscv/bump_env
Megan Wachs [Thu, 21 Dec 2017 23:35:15 +0000 (15:35 -0800)]
Merge pull request #110 from riscv/bump_env

tests: bump env to pick up new names for CSRs

3 years agotests: bump env to pick up new names for CSRs
Megan Wachs [Thu, 21 Dec 2017 23:23:38 +0000 (15:23 -0800)]
tests: bump env to pick up new names for CSRs

3 years agoRemove `set arch riscv:rv%d`
Tim Newsome [Wed, 20 Dec 2017 23:00:01 +0000 (15:00 -0800)]
Remove `set arch riscv:rv%d`

gdb gets target XLEN from register width now, so this is taken care of
automatically.

3 years agoVerify that F18 does not exist on FPU-less targets
Tim Newsome [Wed, 20 Dec 2017 20:17:05 +0000 (12:17 -0800)]
Verify that F18 does not exist on FPU-less targets

3 years agoDisplay env variables used when invoking OpenOCD
Tim Newsome [Tue, 12 Dec 2017 16:02:38 +0000 (08:02 -0800)]
Display env variables used when invoking OpenOCD

This makes it a little easier to just cut and paste from the log when
reproducing a failure. (The port number still needs changing though.)

3 years agoEnsure there are no unnamed registers.
Tim Newsome [Fri, 1 Dec 2017 22:29:11 +0000 (14:29 -0800)]
Ensure there are no unnamed registers.

3 years agoMerge pull request #109 from riscv/vcssim
Tim Newsome [Thu, 30 Nov 2017 20:24:32 +0000 (12:24 -0800)]
Merge pull request #109 from riscv/vcssim

Clean up VcsSim init()

3 years agoClean up VcsSim init()
Tim Newsome [Thu, 30 Nov 2017 19:50:18 +0000 (11:50 -0800)]
Clean up VcsSim init()

Use a unique log file, so you can run multiple instances at once.
Add time out to waiting for the simulator to be ready.

3 years agoRename sbadaddr to satp
Andrew Waterman [Mon, 27 Nov 2017 22:37:58 +0000 (14:37 -0800)]
Rename sbadaddr to satp

3 years agoRv32ud tests (#108)
Torbjørn [Mon, 27 Nov 2017 05:56:53 +0000 (06:56 +0100)]
Rv32ud tests (#108)

* Probably implemented the changes required to support fadd test for rv32ud

* Created test files in rv32ud, implemented working(?) test for ldst

* fclass, fcvt_w, fmin and recoding seem to be working now

* Got fdiv (and sqrt) tests working

* fmadd tests seem to work

* fcmp works

* [WIP] fcvt working, but lacks a 32-bit implementation of the final test

* Renamed macro TEST_LDST_D32 to TEST_CASE_D32 to indicate that it can be used for more than just LDST

* Added Makefrag for rv32ud tests and included in main isa Makefile

* Don't run 64-bit tests if the defined XLEN is 32

3 years agoCheck sepc for rv64si/scall test. (#107)
Christopher Celio [Wed, 22 Nov 2017 22:01:26 +0000 (14:01 -0800)]
Check sepc for rv64si/scall test. (#107)

Closes #105.

3 years agoCheck mtval in rv64mi-p-illegal (#104)
Andrew Waterman [Mon, 20 Nov 2017 19:59:28 +0000 (11:59 -0800)]
Check mtval in rv64mi-p-illegal (#104)

Closes #103

3 years agoEnsure log file is fully written before reading it
Tim Newsome [Mon, 20 Nov 2017 04:54:33 +0000 (20:54 -0800)]
Ensure log file is fully written before reading it

Fixes --print-failures sometimes not actually printing out details about
failures.

3 years agoMake pylint happy.
Tim Newsome [Mon, 20 Nov 2017 04:54:14 +0000 (20:54 -0800)]
Make pylint happy.

3 years agoMerge pull request #102 from riscv/xlen_fix
Megan Wachs [Fri, 17 Nov 2017 21:43:33 +0000 (13:43 -0800)]
Merge pull request #102 from riscv/xlen_fix

debug: Fix the XLEN command line check

3 years agodebug: Fix the XLEN command line check
Megan Wachs [Fri, 17 Nov 2017 19:27:04 +0000 (11:27 -0800)]
debug: Fix the XLEN command line check

3 years agoDebug: Use the --32 and --64 command line arguments (#97)
Megan Wachs [Fri, 17 Nov 2017 00:34:02 +0000 (16:34 -0800)]
Debug: Use the --32 and --64 command line arguments (#97)

* Debug: Actually use the --32 and --64 command line arguments

* debug: make XLEN mismatch message clearer

3 years agoDisable PMP for PrivRw test.
Tim Newsome [Thu, 16 Nov 2017 23:40:27 +0000 (15:40 -0800)]
Disable PMP for PrivRw test.

3 years agoClarify PrivTest detail.
Tim Newsome [Thu, 16 Nov 2017 00:51:49 +0000 (16:51 -0800)]
Clarify PrivTest detail.

3 years agoMake sure that code is 4-byte aligned before disabling rvc (#100)
Andrew Waterman [Sun, 12 Nov 2017 00:15:22 +0000 (16:15 -0800)]
Make sure that code is 4-byte aligned before disabling rvc (#100)

3 years agoMake rv64mi-p-ecall work when U-mode is not present
Andrew Waterman [Fri, 10 Nov 2017 03:25:22 +0000 (19:25 -0800)]
Make rv64mi-p-ecall work when U-mode is not present

3 years agoUse mstatus.MPP to check existence of U-mode
Andrew Waterman [Fri, 10 Nov 2017 01:12:49 +0000 (17:12 -0800)]
Use mstatus.MPP to check existence of U-mode

misa is allowed to be hardwired to 0, so checking its U bit could
incorrectly suggest that U-mode is not supported.

3 years agoAdd --print-log-names to print temp log names ASAP
Tim Newsome [Thu, 2 Nov 2017 22:14:40 +0000 (15:14 -0700)]
Add --print-log-names to print temp log names ASAP

When not passed, they are no longer printed out.

3 years agoEnsure gdb connection failures end up in main log.
Tim Newsome [Thu, 2 Nov 2017 20:11:50 +0000 (13:11 -0700)]
Ensure gdb connection failures end up in main log.

3 years agodebug: Need to apply remotetimeout before connecting to remote target (#94)
Megan Wachs [Thu, 2 Nov 2017 15:46:24 +0000 (08:46 -0700)]
debug: Need to apply remotetimeout before connecting to remote target (#94)

* debug: Need to apply remotetimeout before connecting to remote target

* debug: whitespace cleanup

3 years agoSBREAK test now checks EPC value. (#92)
Christopher Celio [Wed, 1 Nov 2017 20:46:34 +0000 (13:46 -0700)]
SBREAK test now checks EPC value. (#92)

Closes #89

3 years agoMake pylint 1.6.5 happy.
Tim Newsome [Wed, 1 Nov 2017 19:36:36 +0000 (12:36 -0700)]
Make pylint 1.6.5 happy.

3 years agoTest register aliases in the simple register tests
Tim Newsome [Wed, 1 Nov 2017 19:19:16 +0000 (12:19 -0700)]
Test register aliases in the simple register tests

3 years agoFix MulticoreRegTest.
Tim Newsome [Wed, 1 Nov 2017 18:43:04 +0000 (11:43 -0700)]
Fix MulticoreRegTest.

This test would fail intermittently if gdb on the first hart managed to
set a breakpoint, resume, halt, and clear the breakpoint before the
second hart got a chance to resume.

3 years agoMerge pull request #90 from richardxia/comment-out-multicore-reg-test
Palmer Dabbelt [Tue, 31 Oct 2017 23:07:21 +0000 (16:07 -0700)]
Merge pull request #90 from richardxia/comment-out-multicore-reg-test

Temporarily comment out MulticoreRegTest due to flakiness.

3 years agoTemporarily comment out MulticoreRegTest due to flakiness.
Richard Xia [Tue, 31 Oct 2017 20:19:21 +0000 (13:19 -0700)]
Temporarily comment out MulticoreRegTest due to flakiness.

3 years agoRemove cache miss test from last AMO test. (#88)
Richard Xia [Mon, 30 Oct 2017 22:44:21 +0000 (15:44 -0700)]
Remove cache miss test from last AMO test. (#88)

Follow-up to b68b39031a730ecc155ed87fba2ed5f111d0ab07.

The 64KiB allocated by the code to force a cache miss makes it impossible to run
the test from any memories that are smaller 64KiB, such as scratchpad memories
or LIMs. Since this is trying to test microarchitectural behavior, they don't
belong in these ISA tests anyway.

3 years agoDeclare trap handlers as global symbols. (#87)
Richard Xia [Mon, 30 Oct 2017 19:18:49 +0000 (12:18 -0700)]
Declare trap handlers as global symbols. (#87)

This allows them to be referenced by other files, such as a test environment
that lives in a separate compilation unit.

3 years agoVerify that mtval/stval is written correctly on misaligned fetch
Andrew Waterman [Wed, 20 Sep 2017 17:47:11 +0000 (10:47 -0700)]
Verify that mtval/stval is written correctly on misaligned fetch

3 years agoFix rv64mi-csr for the case where U-mode is not available. (#86)
Richard Xia [Fri, 27 Oct 2017 04:33:49 +0000 (21:33 -0700)]
Fix rv64mi-csr for the case where U-mode is not available. (#86)

3 years agoIncrease dual-core RV64 timeouts.
Tim Newsome [Tue, 24 Oct 2017 18:55:01 +0000 (11:55 -0700)]
Increase dual-core RV64 timeouts.

I need this for CompareSections to pass when I instrument spike to be
really slow.