From a5b7f805c111e14a1478153147a57283a0b9e45d Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 11 Jul 2016 17:41:59 -0700 Subject: [PATCH] Remove vestigial j instruction test; improve jal test --- isa/rv32ui/Makefrag | 2 +- isa/rv32ui/j.S | 49 ------------------------------------- isa/rv32ui/jal.S | 59 +++------------------------------------------ isa/rv64ui/Makefrag | 2 +- isa/rv64ui/j.S | 49 ------------------------------------- isa/rv64ui/jal.S | 23 +++++++++--------- 6 files changed, 16 insertions(+), 168 deletions(-) delete mode 100644 isa/rv32ui/j.S delete mode 100644 isa/rv64ui/j.S diff --git a/isa/rv32ui/Makefrag b/isa/rv32ui/Makefrag index 6cb6c08..7c211f1 100644 --- a/isa/rv32ui/Makefrag +++ b/isa/rv32ui/Makefrag @@ -9,7 +9,7 @@ rv32ui_sc_tests = \ auipc \ beq bge bgeu blt bltu bne \ fence_i \ - j jal jalr \ + jal jalr \ lb lbu lh lhu lw \ lui \ or ori \ diff --git a/isa/rv32ui/j.S b/isa/rv32ui/j.S deleted file mode 100644 index 259a236..0000000 --- a/isa/rv32ui/j.S +++ /dev/null @@ -1,49 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# j.S -#----------------------------------------------------------------------------- -# -# Test j instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Test basic - #------------------------------------------------------------- - - li TESTNUM, 2; - j test_2; - j fail; -test_2: - - #------------------------------------------------------------- - # Test delay slot instructions not executed nor bypassed - #------------------------------------------------------------- - - TEST_CASE( 3, x1, 3, \ - li x1, 1; \ - j 1f; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ -1: addi x1, x1, 1; \ - addi x1, x1, 1; \ - ) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv32ui/jal.S b/isa/rv32ui/jal.S index 742abac..93f407b 100644 --- a/isa/rv32ui/jal.S +++ b/isa/rv32ui/jal.S @@ -1,60 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# jal.S -#----------------------------------------------------------------------------- -# -# Test jal instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Test 2: Basic test - #------------------------------------------------------------- - -test_2: - li TESTNUM, 2 - li ra, 0 - -linkaddr_2: - jal target_2 - nop - nop - - j fail - -target_2: - la x2, linkaddr_2 - addi x2, x2, 4 - bne x2, ra, fail - - #------------------------------------------------------------- - # Test delay slot instructions not executed nor bypassed - #------------------------------------------------------------- - - TEST_CASE( 3, x2, 3, \ - li x2, 1; \ - jal 1f; \ - addi x2, x2, 1; \ - addi x2, x2, 1; \ - addi x2, x2, 1; \ - addi x2, x2, 1; \ -1: addi x2, x2, 1; \ - addi x2, x2, 1; \ - ) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/jal.S" diff --git a/isa/rv64ui/Makefrag b/isa/rv64ui/Makefrag index 7920b99..aeeb560 100644 --- a/isa/rv64ui/Makefrag +++ b/isa/rv64ui/Makefrag @@ -9,7 +9,7 @@ rv64ui_sc_tests = \ beq bge bgeu blt bltu bne \ example simple \ fence_i \ - j jal jalr \ + jal jalr \ lb lbu lh lhu lw lwu ld \ lui \ or ori \ diff --git a/isa/rv64ui/j.S b/isa/rv64ui/j.S deleted file mode 100644 index a7e3fe6..0000000 --- a/isa/rv64ui/j.S +++ /dev/null @@ -1,49 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# j.S -#----------------------------------------------------------------------------- -# -# Test j instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Test basic - #------------------------------------------------------------- - - li TESTNUM, 2; - j test_2; - j fail; -test_2: - - #------------------------------------------------------------- - # Test delay slot instructions not executed nor bypassed - #------------------------------------------------------------- - - TEST_CASE( 3, x1, 3, \ - li x1, 1; \ - j 1f; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ -1: addi x1, x1, 1; \ - addi x1, x1, 1; \ - ) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64ui/jal.S b/isa/rv64ui/jal.S index 90d06e9..f7f299d 100644 --- a/isa/rv64ui/jal.S +++ b/isa/rv64ui/jal.S @@ -21,8 +21,8 @@ test_2: li TESTNUM, 2 li ra, 0 + jal x3, target_2 linkaddr_2: - jal target_2 nop nop @@ -30,22 +30,21 @@ linkaddr_2: target_2: la x2, linkaddr_2 - addi x2, x2, 4 - bne x2, ra, fail + bne x2, x3, fail #------------------------------------------------------------- # Test delay slot instructions not executed nor bypassed #------------------------------------------------------------- - TEST_CASE( 3, x2, 3, \ - li x2, 1; \ - jal 1f; \ - addi x2, x2, 1; \ - addi x2, x2, 1; \ - addi x2, x2, 1; \ - addi x2, x2, 1; \ -1: addi x2, x2, 1; \ - addi x2, x2, 1; \ + TEST_CASE( 3, ra, 3, \ + li ra, 1; \ + jal x0, 1f; \ + addi ra, ra, 1; \ + addi ra, ra, 1; \ + addi ra, ra, 1; \ + addi ra, ra, 1; \ +1: addi ra, ra, 1; \ + addi ra, ra, 1; \ ) TEST_PASSFAIL -- 2.30.2