From f1d87fd119cbdca5c5f2016e0a156ac4f0d2347d Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Wed, 6 Apr 2016 10:22:20 -0700
Subject: [PATCH] Fix expected misa register value for RV32

---
 isa/rv64mi/mcsr.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/isa/rv64mi/mcsr.S b/isa/rv64mi/mcsr.S
index 2eeb14c..4bb0445 100644
--- a/isa/rv64mi/mcsr.S
+++ b/isa/rv64mi/mcsr.S
@@ -17,7 +17,7 @@ RVTEST_CODE_BEGIN
 #ifdef __riscv64
   TEST_CASE(2, a0, 0x2, csrr a0, misa; srl a0, a0, 62)
 #else
-  TEST_CASE(2, a0, 0x0, csrr a0, misa; srl a0, a0, 30)
+  TEST_CASE(2, a0, 0x1, csrr a0, misa; srl a0, a0, 30)
 #endif
 
   # Check that mhartid reports 0
-- 
2.30.2