git.libre-soc.org Git - riscv-tests.git/search

2018-05-01	Christopher Celio	[rv64ua/lrsc] Initialize memory read out. (#135)	commit \| commitdiff \| tree
2017-11-22	Christopher Celio	Check sepc for rv64si/scall test. (#107)	commit \| commitdiff \| tree
2017-11-01	Christopher Celio	SBREAK test now checks EPC value. (#92)	commit \| commitdiff \| tree
2015-07-01	Christopher Celio	Add _hard_float check in crt.S.	commit \| commitdiff \| tree
2015-02-24	Christopher Celio	Added more +/- NaN/inf tests for fcvt.{w/l/wu/lu}....	commit \| commitdiff \| tree
2015-02-23	Christopher Celio	Added -NaN test for fcvt.{w/h}.s	commit \| commitdiff \| tree
2014-09-10	Christopher Celio	Enable interrupts in bmarks	commit \| commitdiff \| tree
2014-08-28	Christopher Celio	Added "simple" test to rv32ui.	commit \| commitdiff \| tree
2014-04-18	Christopher Celio	Added a new test case to REMW.	commit \| commitdiff \| tree
2013-10-10	Christopher Celio	Merge branch 'master' of github.com:ucb-bar/riscv-tests	commit \| commitdiff \| tree
2013-10-10	Christopher Celio	Benchmarks now run in user-mode.	commit \| commitdiff \| tree