2018-09-24 Andrew Watermanbump env master
2018-09-13 Tim NewsomeAssert if HiFive1 program is too large.
2018-09-13 Tim NewsomePut debug test stack in data instead of text
2018-09-08 Andrew WatermanMerge branch 'tommythorn-master'
2018-09-08 Tommy ThornRV64 s{ll,ra,rl}w tests with non-canonical values
2018-09-07 Andrew WatermanRevert "breakpoint.S: Don't assume trigger is hardwired...
2018-09-06 Tommy Thornbreakpoint.S: Don't assume trigger is hardwired to...
2018-09-03 Tim NewsomeMerge pull request #156 from riscv/PrivChange
2018-08-31 Tim NewsomeFix CustomRegisterTest.
2018-08-29 Tim NewsomeAdd test case for `riscv expose_custom`.
2018-08-28 Tim NewsomeReset address translation/perms before PrivChange
2018-08-28 Tim NewsomeNeuter TriggerStoreAddressInstant
2018-08-27 Tim NewsomeMake pylint happy.
2018-08-25 Andrew WatermanTemporarily disabling PrivChange test
2018-08-24 Tim NewsomeMake pylint happy with change d1d2d953b5016b465.
2018-08-24 Tim NewsomeGet all of the log into the final log file
2018-08-23 Tim NewsomeMerge pull request #153 from dmitryryzhov/rtos-switch...
2018-08-22 Tim NewsomeMerge branch 'master' of https://github.com/riscv/riscv...
2018-08-22 Tim NewsomeDisable MulticoreRunHaltStepiTest
2018-08-22 Dmitry RyzhovAdd debug test, which checks that openocd correctly...
2018-08-21 Srivatsa YogendraChanging the register mstatus is read into (#152)
2018-08-21 Andrew WatermanRevert "Fix to solve the failing tests shamt, csr and...
2018-08-18 Srivatsa YogendraFix to solve the failing tests shamt, csr and scall...
2018-08-17 Srivatsa Yogendramaking mtvec_handler global (#150)
2018-08-13 Tim NewsomeAdd jump/hbreak test.
2018-07-09 Andrew WatermanCheck that SC yields the load reservation
2018-07-03 Tim Newsomerwatch/watch on explicit address
2018-06-18 Tim NewsomeAdd reproduce line to the end of debug test logs
2018-05-21 Tim NewsomeMerge pull request #141 from riscv/mrhstest
2018-05-19 Tim NewsomeFix MulticoreRunHaltStepiTest
2018-05-15 Megan WachsMerge pull request #139 from riscv/debug-tests-more...
2018-05-14 Megan WachsMerge remote-tracking branch 'origin/downloadtest'...
2018-05-14 Tim NewsomeMake DownloadTest properly park other harts.
2018-05-14 Megan Wachsdebug: remove some unintentionally added newlines
2018-05-14 Megan Wachsdebug: Fixing the non-RTOS behavior for DownloadTest
2018-05-11 Megan Wachsdebug: mark more tests as single-hart tests
2018-05-11 Megan Wachsdebug: output some more useful info into the post-morte...
2018-05-01 Christopher... [rv64ua/lrsc] Initialize memory read out. (#135)
2018-04-30 Tim NewsomeFix formatting to make pylint happy.
2018-04-29 Megan WachsMerge pull request #132 from riscv/debug-clear-satp
2018-04-27 Megan Wachsdebug: need to clear satp before changing priv
2018-04-27 Megan WachsMerge pull request #125 from riscv/debug-delete-sim
2018-04-27 Megan WachsMerge pull request #130 from riscv/trap_entry_align-1
2018-04-27 Megan Wachsdebug: add missing align directive on trap_entry
2018-04-24 Tim NewsomeFix race when making logs directory
2018-04-19 Megan WachsDelete E300Sim.py
2018-04-16 Tim NewsomeMerge pull request #123 from riscv/gdb_timeout
2018-04-09 Tim NewsomeCompute gdb command timeout based on ops estimate
2018-04-09 Andrei TatarnikovFix #120: Instructions 'sll' are replaced with 'slli...
2018-04-02 Tim NewsomeUse `gdb_report_register_access_error enable`
2018-03-27 Tim NewsomeTest debug authentication.
2018-03-23 Tim NewsomePrint log filename at the end of the log.
2018-03-21 Andrew WatermanMake misa.C test conform to Hauser proposal
2018-03-21 Palmer DabbeltMerge pull request #119 from rishikhan/master
2018-03-19 rishiUpdate Makefile to allow for RISCV_PREFIX to be set...
2018-03-01 Tim NewsomeTest debugging with/without a program buffer
2018-03-01 Tim NewsomeEnsure an error when reading a non-existent CSR.
2018-02-27 Andrew WatermanAdd test for clearing misa.C while PC is misaligned...
2018-02-09 Tim NewsomeTest resuming from a trigger.
2018-02-07 Tim NewsomeLink scripts shouldn't be executable.
2018-01-08 Tim NewsomeDeal with gdb reporting pmpcfg0 not existing.
2018-01-05 Tim NewsomeAdd test for multicore failure
2018-01-03 Andrew WatermanTest access exception behavior for illegal addresses...
2017-12-27 Tim NewsomeTest FPRs that aren't XLEN in size.
2017-12-22 Tim NewsomeAdd all-tests target.
2017-12-21 Megan WachsMerge pull request #110 from riscv/bump_env
2017-12-21 Megan Wachstests: bump env to pick up new names for CSRs
2017-12-20 Tim NewsomeRemove `set arch riscv:rv%d`
2017-12-20 Tim NewsomeVerify that F18 does not exist on FPU-less targets
2017-12-12 Tim NewsomeDisplay env variables used when invoking OpenOCD
2017-12-01 Tim NewsomeEnsure there are no unnamed registers.
2017-11-30 Tim NewsomeMerge pull request #109 from riscv/vcssim
2017-11-30 Tim NewsomeClean up VcsSim init()
2017-11-27 Andrew WatermanRename sbadaddr to satp
2017-11-27 TorbjørnRv32ud tests (#108)
2017-11-22 Christopher... Check sepc for rv64si/scall test. (#107)
2017-11-20 Andrew WatermanCheck mtval in rv64mi-p-illegal (#104)
2017-11-20 Tim NewsomeEnsure log file is fully written before reading it
2017-11-20 Tim NewsomeMake pylint happy.
2017-11-17 Megan WachsMerge pull request #102 from riscv/xlen_fix
2017-11-17 Megan Wachsdebug: Fix the XLEN command line check
2017-11-17 Megan WachsDebug: Use the --32 and --64 command line arguments...
2017-11-16 Tim NewsomeDisable PMP for PrivRw test.
2017-11-16 Tim NewsomeClarify PrivTest detail.
2017-11-12 Andrew WatermanMake sure that code is 4-byte aligned before disabling...
2017-11-10 Andrew WatermanMake rv64mi-p-ecall work when U-mode is not present
2017-11-10 Andrew WatermanUse mstatus.MPP to check existence of U-mode
2017-11-02 Tim NewsomeAdd --print-log-names to print temp log names ASAP
2017-11-02 Tim NewsomeEnsure gdb connection failures end up in main log.
2017-11-02 Megan Wachsdebug: Need to apply remotetimeout before connecting...
2017-11-01 Christopher... SBREAK test now checks EPC value. (#92)
2017-11-01 Tim NewsomeMake pylint 1.6.5 happy.
2017-11-01 Tim NewsomeTest register aliases in the simple register tests
2017-11-01 Tim NewsomeFix MulticoreRegTest.
2017-10-31 Palmer DabbeltMerge pull request #90 from richardxia/comment-out...
2017-10-31 Richard XiaTemporarily comment out MulticoreRegTest due to flakiness.
2017-10-30 Richard XiaRemove cache miss test from last AMO test. (#88)
2017-10-30 Richard XiaDeclare trap handlers as global symbols. (#87)
2017-10-27 Andrew WatermanVerify that mtval/stval is written correctly on misalig...
2017-10-27 Richard XiaFix rv64mi-csr for the case where U-mode is not availab...