block_memory_16kbit.v

   1 /*
   2  * Copyright 2018 Jacob Lifshay
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a copy
   5  * of this software and associated documentation files (the "Software"), to deal
   6  * in the Software without restriction, including without limitation the rights
   7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   8  * copies of the Software, and to permit persons to whom the Software is
   9  * furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in all
  12  * copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  17  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  *
  22  */
  23 `timescale 1ns / 1ps
  24 module block_memory_16kbit(
  25     input clk,
  26     input [10:0] port_a_address,
  27     input port_a_write_enable,
  28     input [7:0] port_a_write_input,
  29     output [7:0] port_a_read_output,
  30     input [10:0] port_b_address,
  31     output [7:0] port_b_read_output
  32     );
  33
  34     parameter initial_file = "";
  35
  36     (* ram_style = "block" *)
  37     reg [7:0] ram[{11{1'b1}} : 0];
  38
  39     initial $readmemh(initial_file, ram);
  40
  41     reg [7:0] port_a_read_output_reg;
  42     reg [7:0] port_b_read_output_reg;
  43
  44     always @(posedge clk) begin
  45         port_b_read_output_reg <= ram[port_b_address];
  46         if(port_a_write_enable) begin
  47             ram[port_a_address] <= port_a_write_input;
  48         end
  49         else begin
  50             port_a_read_output_reg <= ram[port_a_address];
  51         end
  52     end
  53
  54     assign port_a_read_output = port_a_read_output_reg;
  55     assign port_b_read_output = port_b_read_output_reg;
  56
  57 endmodule