3 * Copyright 2018 Jacob Lifshay
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in all
13 * copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 from migen
.fhdl
import verilog
32 from migen
.fhdl
.structure
import _Operator
34 from riscvdefs
import *
37 class CPUFetchAction(Module
):
40 self
.action
= Signal(fetch_action
)
41 self
.output_state
= Signal()
42 self
.dc_act
= Signal(decode_action
)
43 self
.load_store_misaligned
= Signal()
44 self
.mi_rw_wait
= Signal()
45 self
.mi_rw_address_valid
= Signal()
46 self
.branch_taken
= Signal()
47 self
.misaligned_jump_target
= Signal()
48 self
.csr_op_is_valid
= Signal()
51 c
["default"] = self
.action
.eq(FA
.default
) # XXX should be 32'XXXXXXXX?
52 c
[FOS
.empty
] = self
.action
.eq(FA
.default
)
53 c
[FOS
.trap
] = self
.action
.eq(FA
.ack_trap
)
55 # illegal instruction -> error trap
56 i
= If((self
.dc_act
& DA
.trap_illegal_instruction
) != 0,
57 self
.action
.eq(FA
.error_trap
)
60 # ecall / ebreak -> noerror trap
61 i
= i
.Elif((self
.dc_act
& DA
.trap_ecall_ebreak
) != 0,
62 self
.action
.eq(FA
.noerror_trap
))
64 # load/store: check alignment, check wait
65 i
= i
.Elif((self
.dc_act
& (DA
.load | DA
.store
)) != 0,
66 If((self
.load_store_misaligned | ~self
.mi_rw_address_valid
),
67 self
.action
.eq(FA
.error_trap
) # misaligned or invalid addr
68 ).Elif(self
.mi_rw_wait
,
69 self
.action
.eq(FA
.wait
) # wait
71 self
.action
.eq(FA
.default
) # ok
76 i
= i
.Elif((self
.dc_act
& DA
.fence
) != 0,
77 self
.action
.eq(FA
.fence
))
79 # branch -> misaligned=error, otherwise jump
80 i
= i
.Elif((self
.dc_act
& DA
.branch
) != 0,
82 If(self
.misaligned_jump_target
,
83 self
.action
.eq(FA
.error_trap
)
85 self
.action
.eq(FA
.jump
)
88 self
.action
.eq(FA
.default
)
92 # jal/jalr -> misaligned=error, otherwise jump
93 i
= i
.Elif((self
.dc_act
& (DA
.jal | DA
.jalr
)) != 0,
94 If(self
.misaligned_jump_target
,
95 self
.action
.eq(FA
.error_trap
)
97 self
.action
.eq(FA
.jump
)
101 # csr -> opvalid=ok, else error trap
102 i
= i
.Elif((self
.dc_act
& DA
.csr
) != 0,
103 If(self
.csr_op_is_valid
,
104 self
.action
.eq(FA
.default
)
106 self
.action
.eq(FA
.error_trap
)
112 self
.comb
+= Case(self
.output_state
, c
)
115 if __name__
== "__main__":
116 example
= CPUFetchAction()
117 print(verilog
.convert(example
,
120 example
.output_state
,
122 example
.load_store_misaligned
,
124 example
.mi_rw_address_valid
,
125 example
.branch_taken
,
126 example
.misaligned_jump_target
,
127 example
.csr_op_is_valid
,