main.v

   1 /*
   2  * Copyright 2018 Jacob Lifshay
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a copy
   5  * of this software and associated documentation files (the "Software"), to deal
   6  * in the Software without restriction, including without limitation the rights
   7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   8  * copies of the Software, and to permit persons to whom the Software is
   9  * furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in all
  12  * copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  17  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  *
  22  */
  23 `timescale 1ns / 100ps
  24
  25 module main(
  26     input clk,
  27     output [7:0] vga_r,
  28         output [7:0] vga_g,
  29         output [7:0] vga_b,
  30         output vga_hsync,
  31         output vga_vsync,
  32     output vga_blank,
  33     output vga_pixel_clock,
  34     input switch_2,
  35     input switch_3,
  36     output led_1,
  37     output led_3
  38     );
  39
  40     wire tty_write;
  41     wire [7:0] tty_write_data;
  42     wire tty_write_busy;
  43     reg reset = 1;
  44
  45         vga vga1(
  46         .clk(clk),
  47         .vga_r(vga_r),
  48         .vga_g(vga_g),
  49         .vga_b(vga_b),
  50         .vga_hsync(vga_hsync),
  51         .vga_vsync(vga_vsync),
  52         .vga_blank(vga_blank),
  53         .vga_pixel_clock(vga_pixel_clock),
  54         .tty_write(tty_write),
  55         .tty_data(tty_write_data),
  56         .tty_busy(tty_write_busy)
  57         );
  58
  59     cpu cpu1(
  60         .clk(clk),
  61         .reset(reset),
  62         .tty_write(tty_write),
  63         .tty_write_data(tty_write_data),
  64         .tty_write_busy(tty_write_busy),
  65         .switch_2(switch_2),
  66         .switch_3(switch_3),
  67         .led_1(led_1),
  68         .led_3(led_3)
  69         );
  70
  71     reg [31:0] reset_counter = 256;
  72
  73     always @(posedge clk)
  74         if(reset_counter == 0)
  75             reset <= 0;
  76         else
  77             reset_counter <= reset_counter - 1;
  78
  79 endmodule