vga_location_generator.v

   1 /*
   2  * Copyright 2018 Jacob Lifshay
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a copy
   5  * of this software and associated documentation files (the "Software"), to deal
   6  * in the Software without restriction, including without limitation the rights
   7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   8  * copies of the Software, and to permit persons to whom the Software is
   9  * furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in all
  12  * copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  17  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  *
  22  */
  23 `timescale 1ns / 100ps
  24
  25 module vga_location_generator(
  26     input pixel_clock,
  27         output reg hsync,
  28         output reg vsync,
  29     output reg blank,
  30     output reg [15:0] x,
  31     output reg [15:0] y,
  32     output reg xy_in_active
  33     );
  34
  35         parameter x_front_porch = 56;
  36         parameter x_active = 800;
  37         parameter x_back_porch = 64;
  38         parameter x_sync = 120;
  39         parameter y_front_porch = 37;
  40         parameter y_active = 600;
  41         parameter y_back_porch = 23;
  42         parameter y_sync = 6;
  43
  44     wire x_at_end = (x == x_active + x_back_porch + x_sync + x_front_porch);
  45     wire y_at_end = (y == y_active + y_back_porch + y_sync + y_front_porch);
  46     wire [15:0] next_x = x_at_end ? 0 : x + 1;
  47     wire [15:0] next_y = x_at_end ? (y_at_end ? 0 : y + 1) : y;
  48     wire next_xy_in_active = (next_x < x_active) & (next_y < y_active);
  49
  50     initial begin
  51         hsync = 0;
  52         vsync = 0;
  53         blank = 0;
  54         x = 0;
  55         y = 0;
  56     end
  57
  58         always @(posedge pixel_clock) begin
  59                 x <= next_x;
  60         y <= next_y;
  61         blank <= next_xy_in_active;
  62         hsync <= ((x >= x_active + x_back_porch) & (x < x_active + x_back_porch + x_sync));
  63         vsync <= ((y >= y_active + y_back_porch) & (y < y_active + y_back_porch + y_sync));
  64         xy_in_active <= next_xy_in_active;
  65         end
  66 endmodule