self.output_instruction = Signal(32, name="fetch_ouutput_instruction")
self.output_state = Signal(fetch_output_state,name="fetch_output_state")
- def get_fetch_action(self, dc_act, load_store_misaligned, mi_rw_wait,
- mi_rw_address_valid,
- branch_taken, misaligned_jump_target,
- csr_op_is_valid):
- c = {}
- c["default"] = self.action.eq(FA.default) # XXX should be 32'XXXXXXXX?
- c[FOS.empty] = self.action.eq(FA.default)
- c[FOS.trap] = self.action.eq(FA.ack_trap)
-
- # illegal instruction -> error trap
- i= If((dc_act & DA.trap_illegal_instruction) != 0,
- self.action.eq(FA.error_trap)
- )
-
- # ecall / ebreak -> noerror trap
- i = i.Elif((dc_act & DA.trap_ecall_ebreak) != 0,
- self.action.eq(FA.noerror_trap))
-
- # load/store: check alignment, check wait
- i = i.Elif((dc_act & (DA.load | DA.store)) != 0,
- If((load_store_misaligned | ~mi_rw_address_valid),
- self.action.eq(FA.error_trap) # misaligned or invalid addr
- ).Elif(mi_rw_wait,
- self.action.eq(FA.wait) # wait
- ).Else(
- self.action.eq(FA.default) # ok
- )
- )
-
- # fence
- i = i.Elif((dc_act & DA.fence) != 0,
- self.action.eq(FA.fence))
-
- # branch -> misaligned=error, otherwise jump
- i = i.Elif((dc_act & DA.branch) != 0,
- If(branch_taken,
- If(misaligned_jump_target,
- self.action.eq(FA.error_trap)
- ).Else(
- self.action.eq(FA.jump)
- )
- ).Else(
- self.action.eq(FA.default)
- )
- )
-
- # jal/jalr -> misaligned=error, otherwise jump
- i = i.Elif((dc_act & (DA.jal | DA.jalr)) != 0,
- If(misaligned_jump_target,
- self.action.eq(FA.error_trap)
- ).Else(
- self.action.eq(FA.jump)
- )
- )
-
- # csr -> opvalid=ok, else error trap
- i = i.Elif((dc_act & DA.csr) != 0,
- If(csr_op_is_valid,
- self.action.eq(FA.default)
- ).Else(
- self.action.eq(FA.error_trap)
- )
- )
-
- c[FOS.valid] = i
-
- return Case(self.output_state, c)
-
class CSR:
def __init__(self, comb, sync, dc, register_rs1):
self.comb = comb
# CSR decoding
csr = CSR(self.comb, self.sync, dc, self.regs.rs1)
- self.comb += ft.get_fetch_action(dc.act, load_store_misaligned,
- mi.rw_wait, mi.rw_address_valid,
- branch_taken, misaligned_jump_target,
- csr.op_is_valid)
+ fi = Instance("CPUFetchAction", name="cpu_fetch_action",
+ o_fetch_action = ft.action,
+ i_output_state = ft.output_state,
+ i_dc_act = dc.act,
+ i_load_store_misaligned = load_store_misaligned,
+ i_mi_rw_wait = mi.rw_wait,
+ i_mi_rw_address_valid = mi.rw_address_valid,
+ i_branch_taken = branch_taken,
+ i_misaligned_jump_target = misaligned_jump_target,
+ i_csr_op_is_valid = csr.op_is_valid)
+
+ self.specials += fi
minfo = MInfo(self.comb)