add Makefile for verilog compilation

[rv32.git] / cpudefs.py

diff --git a/cpudefs.py b/cpudefs.py
index f4598df6b81511fdd58ddea2e35c91b83250eb0c..b5217f94a203cd4024a169e1902d0aa561282635 100644 (file)
--- a/cpudefs.py
+++ b/cpudefs.py
@@ -39,9 +39,12 @@ class FA:
 
 fetch_output_state = 2
 
-fetch_output_state_empty = Constant(0x0, fetch_output_state)
-fetch_output_state_valid = Constant(0x1, fetch_output_state)
-fetch_output_state_trap = Constant(0x2, fetch_output_state)
+class FOS:
+    """ Fetch output state constants
+    """
+    empty = Constant(0x0, fetch_output_state)
+    valid = Constant(0x1, fetch_output_state)
+    trap = Constant(0x2, fetch_output_state)
 
 decode_action = 12