big reorg, class-ify constants

diff --git a/cpu_decoder.py b/cpu_decoder.py
index d8b4680707124c8562e123f0eaa5ced7ccd159b6..948e10d6a4e1f281d7132c946951f64136bcaa7a 100644 (file)
--- a/cpu_decoder.py
+++ b/cpu_decoder.py
@@ -66,32 +66,32 @@ class CPUDecoder(Module):
         no_imm = 0x0
 
         # R-type: no immediate
-        for op in [opcode_amo, opcode_op, opcode_op_32, opcode_op_fp]:
+        for op in [OP.amo, OP.op, OP.op_32, OP.op_fp]:
             ci[op] = self.immediate.eq(no_imm)
 
-        # I-type
+        # I-type: sign-extended bits 20-31
         im = Cat(self.instruction[20:], Replicate(self.instruction[31], 20))
-        for op in [opcode_load, opcode_load_fp, opcode_misc_mem,
-                   opcode_op_imm, opcode_op_imm_32, opcode_jalr,
-                   opcode_system]:
+        for op in [OP.load, OP.load_fp, OP.misc_mem,
+                   OP.op_imm, OP.op_imm_32, OP.jalr,
+                   OP.system]:
             ci[op] = self.immediate.eq(im)
 
         # S-type
         im = Cat(self.instruction[7:12], self.instruction[25:31],
                  Replicate(self.instruction[31], 21))
-        for op in [opcode_store, opcode_store_fp]:
+        for op in [OP.store, OP.store_fp]:
             ci[op] = self.immediate.eq(im)
 
         # B-type
         im = Cat(Constant(0, 1),
                  self.instruction[8:12], self.instruction[25:31],
                  self.instruction[7], Replicate(self.instruction[31], 20))
-        for op in [opcode_branch, ]:
+        for op in [OP.branch, ]:
             ci[op] = self.immediate.eq(im)
 
         # U-type
         im = Cat(Constant(0, 1), self.instruction[12:], )
-        for op in [opcode_auipc, opcode_lui]:
+        for op in [OP.auipc, OP.lui]:
             ci[op] = self.immediate.eq(im)
 
         # J-type
@@ -99,18 +99,18 @@ class CPUDecoder(Module):
                  self.instruction[21:25], self.instruction[25:31],
                  self.instruction[20], self.instruction[12:20],
                  Replicate(self.instruction[31], 12))
-        for op in [opcode_jal, ]:
+        for op in [OP.jal, ]:
             ci[op] = self.immediate.eq(im)
 
         # R4-type: no immediate
-        for op in [opcode_madd, opcode_msub, opcode_nmsub, opcode_nmadd]:
+        for op in [OP.madd, OP.msub, OP.nmsub, OP.nmadd]:
             ci[op] = self.immediate.eq(no_imm)
 
         # unknown
-        for op in [ opcode_custom_0, opcode_48b_escape_0, opcode_custom_1,
-                    opcode_64b_escape, opcode_reserved_10101, opcode_rv128_0,
-                    opcode_48b_escape_1, opcode_reserved_11010,
-                    opcode_reserved_11101, opcode_rv128_1, opcode_80b_escape]:
+        for op in [ OP.custom_0, OP.op_48b_escape_0, OP.custom_1,
+                    OP.op_64b_escape, OP.reserved_10101, OP.rv128_0,
+                    OP.op_48b_escape_1, OP.reserved_11010,
+                    OP.reserved_11101, OP.rv128_1, OP.op_80b_escape]:
             ci[op] = self.immediate.eq(no_imm)
 
         # default
@@ -119,7 +119,7 @@ class CPUDecoder(Module):
 
         return Case(self.opcode, ci)
 
-    def _decode_funct3(self, options, action):
+    def _decode_funct3(self, action, options):
         """ decode by list of cases
         """
         c = {}
@@ -127,36 +127,31 @@ class CPUDecoder(Module):
         for op in options:
             c[op] = self.decode_action.eq(action)
         # default
-        c["default"] = \
-            self.decode_action.eq(decode_action_trap_illegal_instruction)
+        c["default"] = self.decode_action.eq(DA.trap_illegal_instruction)
 
         return Case(self.funct3, c)
 
     def calculate_store_action(self):
         """ decode store action
         """
-        return self._decode_funct3([ funct3_sb, funct3_sh, funct3_sw, ],
-                                    decode_action_store)
+        return self._decode_funct3(DA.store, [F3.sb, F3.sh, F3.sw, ])
 
     def calculate_load_action(self):
         """ decode load action
         """
-        return self._decode_funct3([ funct3_lb, funct3_lbu, funct3_lh,
-                                     funct3_lhu, funct3_lw, ],
-                                    decode_action_load)
+        return self._decode_funct3(DA.load, [F3.lb, F3.lbu, F3.lh,
+                                             F3.lhu, F3.lw, ])
 
     def calculate_branch_action(self):
         """ decode branch action
         """
-        return self._decode_funct3([ funct3_beq, funct3_bne, funct3_blt,
-                                     funct3_bge, funct3_bltu, funct3_bgeu ],
-                                    decode_action_branch)
+        return self._decode_funct3(DA.branch, [F3.beq, F3.bne, F3.blt,
+                                               F3.bge, F3.bltu, F3.bgeu ])
 
     def calculate_jalr_action(self):
         """ decode jalr action
         """
-        return self._decode_funct3([ funct3_jalr, ],
-                                    decode_action_jalr)
+        return self._decode_funct3(DA.jalr, [F3.jalr, ])
 
     def calculate_op_action(self):
         """ decode op action
@@ -164,22 +159,21 @@ class CPUDecoder(Module):
         c = {}
         immz = Constant(0, 12)
         regz = Constant(0, 5)
-        # fence
-        c[funct3_slli] = \
+        # slli
+        c[F3.slli] = \
             If((self.funct7 == Constant(0, 7)),
-                self.decode_action.eq(decode_action_op_op_imm)).\
-            Else(
-                self.decode_action.eq(decode_action_trap_illegal_instruction))
-        # fence.i
-        c[funct3_srli_srai] = \
+                self.decode_action.eq(DA.op_op_imm)
+            ).Else(
+                self.decode_action.eq(DA.trap_illegal_instruction))
+        # srli/srai
+        c[F3.srli_srai] = \
             If((self.funct7 == Constant(0, 7) | \
                (self.funct7 == Constant(0x20, 7))),
-                self.decode_action.eq(decode_action_op_op_imm)).\
-            Else(
-                self.decode_action.eq(decode_action_trap_illegal_instruction))
+                self.decode_action.eq(DA.op_op_imm)
+            ).Else(
+                self.decode_action.eq(DA.trap_illegal_instruction))
         # default
-        c["default"] = \
-            self.decode_action.eq(decode_action_op_op_imm)
+        c["default"] = self.decode_action.eq(DA.op_op_imm)
 
         return Case(self.funct3, c)
 
@@ -190,22 +184,21 @@ class CPUDecoder(Module):
         immz = Constant(0, 12)
         regz = Constant(0, 5)
         # fence
-        c[funct3_fence] = \
+        c[F3.fence] = \
             If((self.immediate[8:12] == immz) & (self.rs1 == regz) & \
                                                    (self.rd == regz),
-                self.decode_action.eq(decode_action_fence)).\
-            Else(
-                self.decode_action.eq(decode_action_trap_illegal_instruction))
+                self.decode_action.eq(DA.fence)
+            ).Else(
+                self.decode_action.eq(DA.trap_illegal_instruction))
         # fence.i
-        c[funct3_fence_i] = \
+        c[F3.fence_i] = \
             If((self.immediate[0:12] == immz) & (self.rs1 == regz) & \
                                                     (self.rd == regz),
-                self.decode_action.eq(decode_action_fence_i)).\
-            Else(
-                self.decode_action.eq(decode_action_trap_illegal_instruction))
+                self.decode_action.eq(DA.fence_i)
+            ).Else(
+                self.decode_action.eq(DA.trap_illegal_instruction))
         # default
-        c["default"] = \
-            self.decode_action.eq(decode_action_trap_illegal_instruction)
+        c["default"] = self.decode_action.eq(DA.trap_illegal_instruction)
 
         return Case(self.funct3, c)
 
@@ -216,19 +209,18 @@ class CPUDecoder(Module):
         b1 = Constant(1, 32)
         regz = Constant(0, 5)
         # ebreak
-        c[funct3_ecall_ebreak] = \
+        c[F3.ecall_ebreak] = \
             If((self.immediate != ~b1) | (self.rs1 != regz) | \
                                                    (self.rd != regz),
-                self.decode_action.eq(decode_action_trap_illegal_instruction)).\
-            Else(
-                self.decode_action.eq(decode_action_trap_ecall_ebreak))
+                self.decode_action.eq(DA.trap_illegal_instruction)
+            ).Else(
+                self.decode_action.eq(DA.trap_ecall_ebreak))
         # csrs
-        for op in [ funct3_csrrw, funct3_csrrs, funct3_csrrc,
-                    funct3_csrrwi, funct3_csrrsi, funct3_csrrci]:
-            c[op] = self.decode_action.eq(decode_action_csr)
+        for op in [ F3.csrrw, F3.csrrs, F3.csrrc,
+                    F3.csrrwi, F3.csrrsi, F3.csrrci]:
+            c[op] = self.decode_action.eq(DA.csr)
         # default
-        c["default"] = \
-            self.decode_action.eq(decode_action_trap_illegal_instruction)
+        c["default"] = self.decode_action.eq(DA.trap_illegal_instruction)
 
         return Case(self.funct3, c)
 
@@ -240,28 +232,28 @@ class CPUDecoder(Module):
             (funct7 in the case of arith ops).
         """
         c = {}
-        c[opcode_load] = self.calculate_load_action()
-        c[opcode_misc_mem] = self.calculate_misc_action()
-        c[opcode_op_imm] = self.calculate_op_action()
-        c[opcode_op] = self.calculate_op_action()
-        c[opcode_lui] = self.decode_action.eq(decode_action_lui_auipc)
-        c[opcode_auipc] = self.decode_action.eq(decode_action_lui_auipc)
-        c[opcode_store] = self.calculate_store_action()
-        c[opcode_branch] = self.calculate_branch_action()
-        c[opcode_jalr] = self.calculate_jalr_action()
-        c[opcode_jal] = self.decode_action.eq(decode_action_jal)
-        c[opcode_system] = self.calculate_system_action()
+        c[OP.load] = self.calculate_load_action()
+        c[OP.misc_mem] = self.calculate_misc_action()
+        c[OP.op_imm] = self.calculate_op_action()
+        c[OP.op] = self.calculate_op_action()
+        c[OP.lui] = self.decode_action.eq(DA.lui_auipc)
+        c[OP.auipc] = self.decode_action.eq(DA.lui_auipc)
+        c[OP.store] = self.calculate_store_action()
+        c[OP.branch] = self.calculate_branch_action()
+        c[OP.jalr] = self.calculate_jalr_action()
+        c[OP.jal] = self.decode_action.eq(DA.jal)
+        c[OP.system] = self.calculate_system_action()
 
         # big batch of unrecognised opcodes: throw trap.
-        for o in [ opcode_load_fp, opcode_custom_0, opcode_op_imm_32,
-                    opcode_48b_escape_0, opcode_store_fp, opcode_custom_1,
-                    opcode_amo, opcode_op_32, opcode_64b_escape,
-                    opcode_madd, opcode_msub, opcode_nmsub,
-                    opcode_nmadd, opcode_op_fp, opcode_reserved_10101,
-                    opcode_rv128_0, opcode_48b_escape_1, opcode_reserved_11010,
-                    opcode_reserved_11101, opcode_rv128_1, opcode_80b_escape,
+        for o in [ OP.load_fp, OP.custom_0, OP.op_imm_32,
+                    OP.op_48b_escape_0, OP.store_fp, OP.custom_1,
+                    OP.amo, OP.op_32, OP.op_64b_escape,
+                    OP.madd, OP.msub, OP.nmsub,
+                    OP.nmadd, OP.op_fp, OP.reserved_10101,
+                    OP.rv128_0, OP.op_48b_escape_1, OP.reserved_11010,
+                    OP.reserved_11101, OP.rv128_1, OP.op_80b_escape,
                     "default", ]:
-            c[o] = self.decode_action.eq(decode_action_trap_illegal_instruction)
+            c[o] = self.decode_action.eq(DA.trap_illegal_instruction)
 
         return Case(self.opcode, c)
 

diff --git a/cpudefs.py b/cpudefs.py
index 9a58cffa6feead8f7657502f94b6ccd9e78c1d2c..4edab9706e8dba5dd2b8b54fac6e41a65ce1c0e2 100644 (file)
--- a/cpudefs.py
+++ b/cpudefs.py
@@ -42,16 +42,18 @@ fetch_output_state_trap = Constant(0x2, fetch_output_state)
 
 decode_action = 12
 
-decode_action_trap_illegal_instruction = Constant(0x1, decode_action)
-decode_action_load = Constant(0x2, decode_action)
-decode_action_fence = Constant(0x4, decode_action)
-decode_action_fence_i = Constant(0x8, decode_action)
-decode_action_op_op_imm = Constant(0x10, decode_action)
-decode_action_lui_auipc = Constant(0x20, decode_action)
-decode_action_store = Constant(0x40, decode_action)
-decode_action_branch = Constant(0x80, decode_action)
-decode_action_jalr = Constant(0x100, decode_action)
-decode_action_jal = Constant(0x200, decode_action)
-decode_action_trap_ecall_ebreak = Constant(0x400, decode_action)
-decode_action_csr = Constant(0x800, decode_action)
-
+class DA:
+    """ Decode action constants
+    """
+    trap_illegal_instruction = Constant(0x1, decode_action)
+    load = Constant(0x2, decode_action)
+    fence = Constant(0x4, decode_action)
+    fence_i = Constant(0x8, decode_action)
+    op_op_imm = Constant(0x10, decode_action)
+    lui_auipc = Constant(0x20, decode_action)
+    store = Constant(0x40, decode_action)
+    branch = Constant(0x80, decode_action)
+    jalr = Constant(0x100, decode_action)
+    jal = Constant(0x200, decode_action)
+    trap_ecall_ebreak = Constant(0x400, decode_action)
+    csr = Constant(0x800, decode_action)

diff --git a/riscvdefs.py b/riscvdefs.py
index 14267c5be3650d0fe7ab4157d9f97817039fdac1..f00407ab68cbbd6948b5df2c57ebcfb7d7a609db 100644 (file)
--- a/riscvdefs.py
+++ b/riscvdefs.py
@@ -40,88 +40,94 @@ cause_instruction_page_fault = Constant(0xC, 4)
 cause_load_page_fault = Constant(0xD, 4)
 cause_store_amo_page_fault = Constant(0xF, 4)
 
-opcode_load = Constant(0x03, 7)
-opcode_load_fp = Constant(0x07, 7)
-opcode_custom_0 = Constant(0x0B, 7)
-opcode_misc_mem = Constant(0x0F, 7)
-opcode_op_imm = Constant(0x13, 7)
-opcode_auipc = Constant(0x17, 7)
-opcode_op_imm_32 = Constant(0x1B, 7)
-opcode_48b_escape_0 = Constant(0x1F, 7)
-
-opcode_store = Constant(0x23, 7)
-opcode_store_fp = Constant(0x27, 7)
-opcode_custom_1 = Constant(0x2B, 7)
-opcode_amo = Constant(0x2F, 7)
-opcode_op = Constant(0x33, 7)
-opcode_lui = Constant(0x37, 7)
-opcode_op_32 = Constant(0x3B, 7)
-opcode_64b_escape = Constant(0x3F, 7)
-
-opcode_madd = Constant(0x43, 7)
-opcode_msub = Constant(0x47, 7)
-opcode_nmsub = Constant(0x4B, 7)
-opcode_nmadd = Constant(0x4F, 7)
-opcode_op_fp = Constant(0x53, 7)
-opcode_reserved_10101 = Constant(0x57, 7)
-opcode_rv128_0 = Constant(0x5B, 7)
-opcode_48b_escape_1 = Constant(0x5F, 7)
-
-opcode_branch = Constant(0x63, 7)
-opcode_jalr = Constant(0x67, 7)
-opcode_reserved_11010 = Constant(0x6B, 7)
-opcode_jal = Constant(0x6F, 7)
-opcode_system = Constant(0x73, 7)
-opcode_reserved_11101 = Constant(0x77, 7)
-opcode_rv128_1 = Constant(0x7B, 7)
-opcode_80b_escape = Constant(0x7F, 7)
-
-funct3_jalr = Constant(0x0, 3)
-funct3_beq = Constant(0x0, 3)
-funct3_bne = Constant(0x1, 3)
-funct3_blt = Constant(0x4, 3)
-funct3_bge = Constant(0x5, 3)
-funct3_bltu = Constant(0x6, 3)
-funct3_bgeu = Constant(0x7, 3)
-
-funct3_lb = Constant(0x0, 3)
-funct3_lh = Constant(0x1, 3)
-funct3_lw = Constant(0x2, 3)
-funct3_lbu = Constant(0x4, 3)
-funct3_lhu = Constant(0x5, 3)
-
-funct3_sb = Constant(0x0, 3)
-funct3_sh = Constant(0x1, 3)
-funct3_sw = Constant(0x2, 3)
-
-funct3_addi = Constant(0x0, 3)
-funct3_slli = Constant(0x1, 3)
-funct3_slti = Constant(0x2, 3)
-funct3_sltiu = Constant(0x3, 3)
-funct3_xori = Constant(0x4, 3)
-funct3_srli_srai = Constant(0x5, 3)
-funct3_ori = Constant(0x6, 3)
-funct3_andi = Constant(0x7, 3)
-
-funct3_add_sub = Constant(0x0, 3)
-funct3_sll = Constant(0x1, 3)
-funct3_slt = Constant(0x2, 3)
-funct3_sltu = Constant(0x3, 3)
-funct3_xor = Constant(0x4, 3)
-funct3_srl_sra = Constant(0x5, 3)
-funct3_or = Constant(0x6, 3)
-funct3_and = Constant(0x7, 3)
-
-funct3_fence = Constant(0x0, 3)
-funct3_fence_i = Constant(0x1, 3)
-
-funct3_ecall_ebreak = Constant(0x0, 3)
-funct3_csrrw = Constant(0x1, 3)
-funct3_csrrs = Constant(0x2, 3)
-funct3_csrrc = Constant(0x3, 3)
-funct3_csrrwi = Constant(0x5, 3)
-funct3_csrrsi = Constant(0x6, 3)
-funct3_csrrci = Constant(0x7, 3)
+class OP:
+    """  Opcode constants
+    """
+    load = Constant(0x03, 7)
+    load_fp = Constant(0x07, 7)
+    custom_0 = Constant(0x0B, 7)
+    misc_mem = Constant(0x0F, 7)
+    op_imm = Constant(0x13, 7)
+    auipc = Constant(0x17, 7)
+    op_imm_32 = Constant(0x1B, 7)
+    op_48b_escape_0 = Constant(0x1F, 7)
+
+    store = Constant(0x23, 7)
+    store_fp = Constant(0x27, 7)
+    custom_1 = Constant(0x2B, 7)
+    amo = Constant(0x2F, 7)
+    op = Constant(0x33, 7)
+    lui = Constant(0x37, 7)
+    op_32 = Constant(0x3B, 7)
+    op_64b_escape = Constant(0x3F, 7)
+
+    madd = Constant(0x43, 7)
+    msub = Constant(0x47, 7)
+    nmsub = Constant(0x4B, 7)
+    nmadd = Constant(0x4F, 7)
+    op_fp = Constant(0x53, 7)
+    reserved_10101 = Constant(0x57, 7)
+    rv128_0 = Constant(0x5B, 7)
+    op_48b_escape_1 = Constant(0x5F, 7)
+
+    branch = Constant(0x63, 7)
+    jalr = Constant(0x67, 7)
+    reserved_11010 = Constant(0x6B, 7)
+    jal = Constant(0x6F, 7)
+    system = Constant(0x73, 7)
+    reserved_11101 = Constant(0x77, 7)
+    rv128_1 = Constant(0x7B, 7)
+    op_80b_escape = Constant(0x7F, 7)
+
+class F3:
+    """ Funct3 constants
+    """
+    jalr = Constant(0x0, 3)
+    beq = Constant(0x0, 3)
+    bne = Constant(0x1, 3)
+    blt = Constant(0x4, 3)
+    bge = Constant(0x5, 3)
+    bltu = Constant(0x6, 3)
+    bgeu = Constant(0x7, 3)
+
+    lb = Constant(0x0, 3)
+    lh = Constant(0x1, 3)
+    lw = Constant(0x2, 3)
+    lbu = Constant(0x4, 3)
+    lhu = Constant(0x5, 3)
+
+    sb = Constant(0x0, 3)
+    sh = Constant(0x1, 3)
+    sw = Constant(0x2, 3)
+
+    addi = Constant(0x0, 3)
+    slli = Constant(0x1, 3)
+    slti = Constant(0x2, 3)
+    sltiu = Constant(0x3, 3)
+    xori = Constant(0x4, 3)
+    srli_srai = Constant(0x5, 3)
+    ori = Constant(0x6, 3)
+    andi = Constant(0x7, 3)
+
+    add_sub = Constant(0x0, 3)
+    sll = Constant(0x1, 3)
+    slt = Constant(0x2, 3)
+    sltu = Constant(0x3, 3)
+    xor = Constant(0x4, 3)
+    srl_sra = Constant(0x5, 3)
+    _or = Constant(0x6, 3)
+    _and = Constant(0x7, 3)
+
+    fence = Constant(0x0, 3)
+    fence_i = Constant(0x1, 3)
+
+    ecall_ebreak = Constant(0x0, 3)
+    csrrw = Constant(0x1, 3)
+    csrrs = Constant(0x2, 3)
+    csrrc = Constant(0x3, 3)
+    csrrwi = Constant(0x5, 3)
+    csrrsi = Constant(0x6, 3)
+    csrrci = Constant(0x7, 3)
 
 csr_ustatus = Constant(0x000, 12)
 csr_fflags = Constant(0x001, 12)