corrections, clash fetch_action and self.fetch_action

diff --git a/cpu_fetch_stage.py b/cpu_fetch_stage.py
index 469b21e48ed9fdb101b909396f0c8322a1c8d6fa..1fa8942f08bb61e275b59e98a3ce19f8f5dfc45c 100644 (file)
--- a/cpu_fetch_stage.py
+++ b/cpu_fetch_stage.py
@@ -55,10 +55,10 @@ class CPUFetchStage(Module):
 
         fetch_pc = Signal(32, reset=reset_vector)
 
-        self.sync += If(fetch_action != fetch_action_wait,
+        self.sync += If(self.fetch_action != fetch_action_wait,
                         self.output_pc.eq(fetch_pc))
 
-        memory_interface_fetch_address = fetch_pc[2:]
+        self.memory_interface_fetch_address = fetch_pc[2:]
 
         #initial output_pc <= reset_vector;
         #initial output_state <= `fetch_output_state_empty;
@@ -75,7 +75,7 @@ class CPUFetchStage(Module):
                     self.output_instruction.eq(self.memory_interface_fetch_data)
                 )
 
-        self.sync += delayed_instruction_valid.eq(fetch_action ==
+        self.sync += delayed_instruction_valid.eq(self.fetch_action ==
                                                   fetch_action_wait)
 
         fc = {
@@ -106,7 +106,8 @@ class CPUFetchStage(Module):
         }
         fc[fetch_action_default] = fc[fetch_action_ack_trap]
         fc[fetch_action_noerror_trap] = fc[fetch_action_error_trap]
-        self.sync += Case(fetch_action, fc).makedefault(fetch_action_default)
+        self.sync += Case(self.fetch_action,
+                          fc).makedefault(fetch_action_default)
 
 if __name__ == "__main__":
     example = CPUFetchStage()