add counters (TODO)

diff --git a/cpu.py b/cpu.py
index c8dafdeb3a10938d0a4d0c34270a07b1e0132b5b..eabe9d85f2157e4ce02c2049e90a8535aaf37243 100644 (file)
--- a/cpu.py
+++ b/cpu.py
@@ -622,6 +622,11 @@ class CPU(Module):
         self.comb += self.get_csr_op_is_valid(csr_op_is_valid, csr_number,
                                               csr_reads, csr_writes)
 
+        # TODO
+        cycle_counter   = Signal(64); # TODO: implement cycle_counter
+        time_counter    = Signal(64); # TODO: implement time_counter
+        instret_counter = Signal(64); # TODO: implement instret_counter
+
 if __name__ == "__main__":
     example = CPU()
     print(verilog.convert(example,