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add Makefile for verilog compilation
[rv32.git]
/
cpu_handle_trap.py
2018-11-28
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2018-11-28
Luke Kenneth Casso...
handle_trap returns values that get manually transferre...
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2018-11-27
Luke Kenneth Casso...
remove trap_handled, remove w_en
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2018-11-27
Luke Kenneth Casso...
move handle trap out to separate module, bit messy
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2018-11-27
Luke Kenneth Casso...
split out cpu handle_trap
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