src/core/core_parameters.bsv

   1 `define RegFileSize 32 // describes the size of ht register file in the processor.
   2 `ifdef spfpu
   3         `define FLEN 32
   4 `endif
   5 `ifdef dpfpu
   6         `define FLEN 64
   7 `endif
   8 //`define fpu_hierarchical //Define this if you want hierarchical modules in verilog
   9
  10 `include "instance_defines.bsv"
  11
  12 //`define MMU
  13 `define PRFDEPTH 6
  14 `ifdef RV64
  15         `define Burst_length_bits 8
  16         `define byte_offset 2
  17         `define DCACHE_ADDR 64
  18         `define DCACHE_BLOCK_SIZE 4
  19         `define DCACHE_WORD_SIZE 8
  20 /////////////////////////////MMU parameters///////////////////////////////////
  21 `define OFFSET  12
  22 `define ASID            8
  23 ///////////////////////////////////////////////////////////////////////////////
  24 ///////////////////////////////////////////////////////////////////////////////
  25         // TLM2 Request Response definitions for Processor to Bus connection
  26         `define TLM_PRM_CPU_REQ 4, 64, 64, 5, Bit #(0)
  27         `define TLM_PRM_CPU_RSP 4, 64, 64, 5, Bit #(0)
  28
  29         // TLM2 Request Response definitions for Memory to Bus connection
  30         `define TLM_PRM_MEM_REQ 4, 64, 64, 5, Bit #(0)
  31         `define TLM_PRM_MEM_RSP 4, 64, 64, 5, Bit #(0)
  32
  33         // Axi Request Response definitions for Processor as a Master
  34         `define AXI_PRM_CPU     4, 64, 64, 5, Bit #(0)  // Fabric Interface
  35         `define AXI_XTR_CPU TLMRequest #(`TLM_PRM_CPU_REQ), TLMResponse #(`TLM_PRM_CPU_RSP), `AXI_PRM_CPU // Transactor Interface
  36
  37         // Axi Request Response definitions for Memory as a Slave
  38         `define AXI_PRM_MEM     4, 64, 64, 5, Bit #(0)  // Fabric Interface
  39         `define AXI_XTR_MEM TLMRequest #(`TLM_PRM_MEM_REQ), TLMResponse #(`TLM_PRM_MEM_RSP), `AXI_PRM_MEM // Transactor Interface
  40 ///////////////////////////////////////////////////////////////////////////////
  41 `else
  42         `define byte_offset 1
  43         `define Addr_width 32 // the address width
  44         `define DCACHE_ADDR 32
  45         `define DCACHE_BLOCK_SIZE 8
  46         `define DCACHE_WORD_SIZE 4
  47 ///////////////////////////////////////////////////////////////////////////////
  48         // TLM2 Request Response definitions for Processor to Bus connection
  49         `define TLM_PRM_CPU_REQ 4, 32, 32, 5, Bit #(0)
  50         `define TLM_PRM_CPU_RSP 4, 32, 32, 5, Bit #(0)
  51
  52         // TLM2 Request Response definitions for Memory to Bus connection
  53         `define TLM_PRM_MEM_REQ 4, 32, 32, 5, Bit #(0)
  54         `define TLM_PRM_MEM_RSP 4, 32, 32, 5, Bit #(0)
  55
  56         // Axi Request Response definitions for Processor as a Master
  57         `define AXI_PRM_CPU     4, 32, 32, 5, Bit #(0)  // Fabric Interface
  58         `define AXI_XTR_CPU TLMRequest #(`TLM_PRM_CPU_REQ), TLMResponse #(`TLM_PRM_CPU_RSP), `AXI_PRM_CPU // Transactor Interface
  59
  60         // Axi Request Response definitions for Memory as a Slave
  61         `define AXI_PRM_MEM     4, 32, 32, 5, Bit #(0)  // Fabric Interface
  62         `define AXI_XTR_MEM TLMRequest #(`TLM_PRM_MEM_REQ), TLMResponse #(`TLM_PRM_MEM_RSP), `AXI_PRM_MEM // Transactor Interface
  63 ///////////////////////////////////////////////////////////////////////////////
  64 `endif
  65
  66 `define Loop 1
  67 `define BAUD_RATE 130
  68 `ifdef verilog
  69         `define Addr_space 22   //since we are leaving off the lower 2 bits of address(byte addressable memory), we have to
  70 `else
  71         `define Addr_space 30
  72 `endif
  73 `ifdef simulate
  74   `define BAUD_RATE 5 //130 //
  75 `endif
  76 `define INTERRUPT_PINS 64
  77
  78 // Branch_predictor_paramters
  79 /////////////////////////// CACHE RELATED PARAMETERS ////////////////////////////////
  80 `define DCACHE_WAYS 4
  81 `define DCACHE_SETS 512
  82
  83 `define ICACHE_WAYS 4                   // way_bits =2
  84 `define ICACHE_BLOCK_SIZE 8     // word_bits = 3
  85 `define ICACHE_SETS 512                 // set_bits     =7
  86 `define ICACHE_WORD_SIZE 4              // byte_bits=2
  87 `define ICACHE_TAG_BITS 20              // tag_bits = 52
  88 `define DCACHE_TAG_BITS 20              // tag_bits = 52
  89 `define BTB_DEPTH                       256
  90 `define RAS_DEPTH                       8
  91 /////////////////////////////////////////////////////////////////////////////////////
  92 `ifdef RV64
  93         `define MISA_BITS   'h141129 //'h082C849//// 'h40101121 // A + F + I + M + U
  94         `define MXL_BITS                'h2
  95 `else
  96         `define MISA_BITS   'h082C849 // 'h40101121 // A + F + I + M + U
  97         `define MXL_BITS                'h1
  98 `endif
  99 `define MTVEC_DEFAULT       'h00000000
 100 `define STVEC_DEFAULT       'h00000000
 101 `define UTVEC_DEFAULT       'h00000000
 102 /////////////////////////// Register Mapping for Machine Mode Regs /////////////////
 103 `define MSTATUS                 'h00 //'h300 // Machine Status register
 104 `define MISA                            'h01 //'h301 // ISA and extensions
 105 `define MEDELEG                 'h02 //'h302 // Machine exception delegation
 106 `define MIDELEG                 'h03 //'h303 // Machine interrupt delegation
 107 `define MIE                                     'h04 //'h304 // Machine interrupt enable
 108 `define MTVEC                           'h05 //'h305 // Machine trap-handler base address
 109 `define MCOUNTEREN              'h06 //'h306 // Machine counter setup register
 110 `define MHPMEVENTSTART  'h23 //'h323 // statr of event selectors
 111 `define MHPMEVENTEND            'h26 //'h326 // end of event selectors
 112 `define MSCRATCH                        'h40 //'h340 // Scratch rgister for machine trap hanglers
 113 `define MEPC                            'h41 //'h341 // Machine exception program counter
 114 `define MCAUSE                          'h42 //'h342 // Machine trap cause
 115 `define MTVAL                           'h43 //'h343 // Machine bad address
 116 `define MIP                                     'h44 //'h344 // Machine interrupt pending
 117 `define MPOWERCONTROL   'h45 //'h345 // 2 bits to control the power switches.
 118 `define PMPCFG0                 'hA0 //'h3A0 //
 119 `ifndef RV64
 120         `define PMPCFG1                 'hA1 //'h3A1 // Physical Memory Protection Configuration Registers
 121 `endif
 122 `define PMPCFG2                 'hA2 //'h3A2 // Physical Memory Protection Configuration Registers
 123 `ifndef RV64
 124         `define PMPCFG3                 'hA3 //'h3A3 // Physical Memory Protection Configuration Registers
 125 `endif
 126 `define PMPADDRSTART 'hB0 //PMP Address array start
 127 `define PMPADDREND   'hB7 //PMP Address array end
 128 `define MCYCLE                          'h00 //'hB00 // Machine cycle counter
 129 `define MTIME                           'h01 //'hB01    // mtime register (Non-standard r/w)
 130 `define MINSTRET                        'h02 //'hB02 // Machine instructions retired.
 131 `define MHPMCOUNTSTART  'h03 //'hB03 // start address for performance counters
 132 `define MHPMCOUNTEND    'h05 //'hB05 // end address for performance counters
 133 `define MTIMECMP                        'h20 //'hB20 //  time compare register (Non-standard r/w)
 134 `define MCYCLEH                 'h80 //'hB80 // Upper 32 bits of mcycle
 135 `define MTIMEH                          'h81 //'hB81    // mtime hi-register (Non-standard r/w)
 136 `define MINSTRETH                       'h82 //'hB82 // Upper 32 bits of minstret.
 137 `define MHPMCOUNTHSTART 'h83 //'hB83 // start address for performance counters higher bits
 138 `define MHPMCOUNTHEND   'h85 //'hB86 // end address for performance counters higher bits
 139 `define MTIMECMPH                       'hA0 //'hBA0 //  time compare hi-register (Non-standard r/w)
 140 `define MHPMTHRESSTART  'hA3 //'hBA3 // start of counter-thresholds
 141 `define MHPMTHRESEND            'hA5 //'hBA6 // end of counter-thresholds
 142 `define MVENDORID                       'h11 //'hF11 // Vendor ID
 143 `define MARCHID                 'h12 //'hF12 // Architecture ID
 144 `define MIMPID                          'h13 //'hF13 // Implementation ID
 145 `define MHARTID                 'h14 //'hF14 // Hardware Thread ID
 146 `define MBOOTSEQ                        'h15 //'hF15 // Hardware Thread ID
 147
 148 `define MHPMTHRESHSTART 'hE0 //'h7E0 // start of counter-thresholds
 149 `define MHPMTHRESHEND   'hE2 //'h7FC // end of counter-thresholds
 150 /////////////////////////// Register Mapping for Supervisor Mode Regs /////////////////
 151 `define SSTATUS     'h00 //'h100 // Supervisor Status register
 152 `define SEDELEG     'h02 //'h102 // Supervisor exception delegation
 153 `define SIDELEG     'h03 //'h103 // Supervisor interrupt delegation
 154 `define SIE         'h04 //'h104 // Supervisor interrupt enable
 155 `define STVEC       'h05 //'h105 // Supervisor trap-handler base address
 156 `define SCOUNTEREN  'h06 //'h106 // Supervisor counter setup register
 157 `define SSCRATCH    'h40 //'h140 // Scratch register for supervisor trap hanglers
 158 `define SEPC        'h41 //'h141 // Supervisor exception program counter
 159 `define SCAUSE      'h42 //'h142 // Supervisor trap cause
 160 `define STVAL             'h43 //'h143 // Supervisor bad address or illegal instruction
 161 `define SIP         'h44 //'h144 // Supervisor interrupt pending
 162 `define SATP        'h80 //'h180 // Supervisor interrupt pending
 163
 164 /////////////////////////// Register Mapping for User Mode Regs /////////////////
 165 `define USTATUS         'h00 //'h000 // User status register
 166 `define FFLAGS                  'h01 //'h001 // FP Accrued exceptions
 167 `define FRM                             'h02 //'h002 // FP Dynamic rounding mode
 168 `define FCSR                    'h03 //'h003 // FP Control and status register
 169 `define UIE                             'h04 //'h004 // User interrupt enable register
 170 `define UTVEC                   'h05 //'h005 // User trap handler base address
 171 `define USCRATCH                'h40 //'h040 // Scratch register for user trap handlers
 172 `define UEPC                    'h41 //'h041 // User exception program counter
 173 `define UCAUSE                  'h42 //'h042 // User trap cause
 174 `define UTVAL                   'h43 //'h043 // User bad address or illegal instruction
 175 `define UIP                             'h44 //'h044 // User interrupt pending
 176 `define UMEMSE                  'h45 //'h045 // Machine Memory Structures enable
 177 `define UCYCLE                  'h00 //'hC00 // cycle counter for RDCYCLE instruction.
 178 `define UTIME                   'h01 //'hC01 // Tiemr for RDTIME instruction
 179 `define UINSTRET                'h02 //'hC02 // Instruction retired counter for RDINSTRET
 180 `define UCYCLEH         'h80 //'hC80 // Upper 32bits of UCYCLE
 181 `define UTIMEH                  'h81 //'hC81 // Upper 32bits of UTIME
 182 `define UINSTRETH               'h82 //'hC82 // Upper 32bits of UINSTRET
 183 `define HPMCOUNTSTART   'h03    //'hC03 // start address for performance counters
 184 `define HPMCOUNTEND             'h05  //'hC06 // start address for performance counters
 185 `define HPMCOUNTHSTART  'h83    //'hC83 // start address for performance counters higher bits
 186 `define HPMCOUNTHEND            'h85  //'hC86 // end address for performance counters higher bits
 187
 188 ////////////////////////////////////////////////////////////////////////////////////
 189 /////////// Debug registers //////////////////////////
 190 `define DCSR            'hb0 //'h7b0
 191 `define DPC                     'hb1 //'h7b1
 192 `define DSCRATCH0       'hb2 //'h7b2
 193 `define DSCRATCH1       'hb3 //'h7b3
 194 `define DENTRY          'hb4 //'h7b4 // holds the address of the debug entry for self loop
 195 `define TSELECT 'ha0 // 'h7a0 // holds the tselect information
 196 `define TDATA1          'ha1 // 'h7a1 // holds the first trigger data
 197 `define TDATA2          'ha2 // 'h7a2 // holds the first trigger data
 198 ////////////////////////////////////////////////////////////////////////////////////
 199 //////////////////////////////////// funct3 defintions for ISA ////////////////////
 200 `define JALR_f3 'b000
 201 `define BEQ_f3  'b000
 202 `define BNE_f3  'b001
 203 `define BLT_f3  'b100
 204 `define BGE_f3  'b101
 205 `define BLTU_f3 'b110
 206 `define BGEU_f3 'b111
 207 `define LB_f3           'b000
 208 `define Lh_f3           'b001
 209 `define LW_f3           'b010
 210 `define LBU_f3  'b100
 211 `define LHU_f3  'b101
 212 `define LWU_f3  'b110
 213 `define SB_f3           'b000
 214 `define SH_f3           'b001
 215 `define SW_f3           'b010
 216 `define ADD_SUB_f3      'b000
 217 `define SLT_SLTI_f3     'b010
 218 `define SLTU_SLTIU_f3   'b011
 219 `define XOR_XORI_f3     'b100
 220 `define OR_ORI_f3       'b110
 221 `define AND_ANDI_f3     'b111
 222 `define SLL_SLLI_f3     'b001
 223 `define SR_SRI_f3       'b101
 224 `define ECALL_f3        'b000
 225 `define EBREAK_f3       'b000
 226 `define CSRRW_f3        'b001
 227 `define CSRRS_f3        'b010
 228 `define CSRRC_f3        'b011
 229 `define CSRRWI_f3       'b101
 230 `define CSRRSI_f3       'b110
 231 `define CSRRCI_f3       'b111
 232 `define MUL_f3          'b000
 233 `define MULH_f3         'b001
 234 `define MULHSU_f3       'b010
 235 `define MULHU_f3        'b011
 236 `define DIV_f3          'b100
 237 `define DIVU_f3         'b101
 238 `define REM_f3          'b110
 239 `define REMU_f3         'b111
 240 `define ATOMIC_f3       'b010
 241 `define FENCE_f3        'b000
 242 `define FENCEI_f3       'b001
 243 /////////////////////////////////////////////////////////////////////////
 244 ////////////////////// opcode definitions of ISA ////////////////////////
 245 `define LUI_op                          'b01101
 246 `define AUIPC_op                        'b00101
 247 `define JAL_op                          'b11011
 248 `define JALR_op                         'b11001
 249 `define BRANCH_op                       'b11000
 250 `define LOAD_op                         'b00000
 251 `define FLOAD_op                        'b00001
 252 `define STORE_op                        'b01000
 253 `define FSTORE_op                       'b01001
 254 `define IMM_ARITH_op    'b00100
 255 `define ARITH_op                        'b01100
 256 `ifdef RV64
 257         `define IMM_ARITHW_op   'b00110
 258         `define ARITHW_op                       'b01110
 259         `define MULDIVW_op              'b01110
 260 `endif
 261 `define CSR_op                          'b11100
 262 `define MULDIV_op                       'b01100
 263 `define ATOMIC_op                       'b01011
 264 `define FMADD_op                'b10000
 265 `define FMSUB_op                        'b10001
 266 `define FNMSUB_op                       'b10010
 267 `define FNMADD_op                       'b10011
 268 `define FLOAT_op                'b10100
 269 `define FENCE_op                        'b00011
 270 //////////////////////////////////////////////////////////////////////////
 271 /////////////// funct7 deifnition of ISA /////////////////////////////////
 272 `define SLLI_f7         'b0000000
 273 `define LOGIC_SHIFT_f7          'b0000000
 274 `define ARITH_SHIFT_f7          'b0100000
 275 `define ARITH_f7                'b0000000
 276 `define SUB_f7                  'b0100000
 277 `define MULDIV_f7               'b0000001
 278 `define SFENCE_VMA      'b0001001
 279 `define LR_f5                           'b00010
 280 `define SC_f5                           'b00011
 281 `define AMOSWAP_f5      'b00001
 282 `define AMOADD_f5               'b00000
 283 `define AMOXOR_f5               'b00100
 284 `define AMOAND_f5               'b01100
 285 `define AMOOR_f5                'b01000
 286 `define AMOMIN_f5               'b10000
 287 `define AMOMAX_f5               'b10100
 288 `define AMOMINU_f5      'b11000
 289 `define AMOMAXU_f5      'b11100
 290 `define AMOMIN_f5       'b10000
 291 `define AMOMAX_f5       'b10100
 292
 293
 294 `define FADD_f5         'b00000
 295 `define FSUB_f5         'b00001
 296 `define FMUL_f5         'b00010
 297 `define FDIV_f5         'b00011
 298 `define FSQRT_f5        'b01011
 299 `define FP_OPCODE       'b0100
 300 `define FCMP_f5         'b10100
 301 `define FMMAX_f5        'b00101
 302 `define FCVT_F_I_f5     'b11010
 303 `define FCVT_I_F_f5     'b11000
 304 `define FSGNJN_f5       'b00100
 305 `define FCLASS_f5       'b11100
 306 `define FCVT_S_D_f5     'b01000
 307 `define FMV_X_S_f7      'b1110000
 308 `define FMV_S_X_f7      'b1111000
 309 `define FMV_X_D_f7      'b1110001
 310 `define FMV_D_X_f7      'b1111001
 311
 312
 313
 314
 315 ///////////////////////////////////////////////////////////////////////////
 316 ///////////////// Event Values of Performance Counters ////////////////////
 317 `define PERFMONITORS                                                    64
 318 `define CYCLECOUNTERS                                           13
 319 `define ICACHE_MISS                                                     0
 320 `define ICACHE_CACHEABLE                                        `ICACHE_MISS+1
 321 `define ICACHE_LINEREPLACE                              `ICACHE_CACHEABLE+1
 322 `define ICACHE_TLBMISS                                          `ICACHE_LINEREPLACE+1
 323 `define ICACHE_MISALIGNED                                       `ICACHE_TLBMISS+1
 324 `define ICACHE_PREFETCHMISS                             `ICACHE_MISALIGNED+1
 325 `define COND_BRANCH                                                     `ICACHE_PREFETCHMISS+1
 326 `define COND_BRANCH_TAKEN                                       `COND_BRANCH+1
 327 `define COND_BRANCH_MISPREDICTED                        `COND_BRANCH_TAKEN+1
 328 `define TAKEN_BRANCH_MISPREDICTED               `COND_BRANCH_MISPREDICTED+1
 329 `define UNCOND_JUMPS                                                    `TAKEN_BRANCH_MISPREDICTED+1
 330 `define SPFPU_INST                                                      `UNCOND_JUMPS+1
 331 `define DPFPU_INST                                                      `SPFPU_INST+1
 332 `define DCACHE_TLBMISS                                          `DPFPU_INST+1
 333 `define TOTAL_LOADS                                                     `DCACHE_TLBMISS+1
 334 `define TOTAL_STORES                                                    `TOTAL_LOADS+1
 335 `define TOTAL_ATOMIC                                                    `TOTAL_STORES+1
 336 `define DCACHE_LOAD_MISS                                        `TOTAL_ATOMIC+1
 337 `define DCACHE_STORE_MISS                                       `DCACHE_LOAD_MISS+1
 338 `define DCACHE_ATOMIC_MISS                                      `DCACHE_STORE_MISS+1
 339 `define DCACHE_CACHEABLE_LOAD                           `DCACHE_ATOMIC_MISS+1
 340 `define DCACHE_CACHEABLE_STORE                  `DCACHE_CACHEABLE_LOAD+1
 341 `define DCACHE_CACHEABLE_ATOMIC                 `DCACHE_CACHEABLE_STORE+1
 342 `define DCACHE_WRITEBACKS                                       `DCACHE_CACHEABLE_ATOMIC+1
 343 `define DCACHE_LINEREPLACE                                      `DCACHE_WRITEBACKS+1
 344 `define DCACHE_MISALIGNED                                       `DCACHE_LINEREPLACE+1
 345 `define EXCEPTIONS_TAKEN                                        `DCACHE_MISALIGNED+1
 346 `define INTERRUPTS_TAKEN                                        `EXCEPTIONS_TAKEN+1
 347 `define MULDIV_INSTRUCTIONS                             `INTERRUPTS_TAKEN+1
 348 `define MEMORY_INSTRUCTIONS                             `MULDIV_INSTRUCTIONS+1
 349 `define EXEC_FLUSHES                                                    `MEMORY_INSTRUCTIONS+1
 350 `define WB_FLUSHES                                                      `EXEC_FLUSHES+1
 351
 352 `define USERMODE_CYCLES                                         30
 353 `define SUPERVISORMODE_CYCLES                           31
 354 `define MACHINEMODE_CYLES                                       32
 355 `define MISPREDICTION_STALLS                            33
 356 `define INTERRUPT_STALLS                                        34
 357 `define DFENCE_CYCLES                                           35
 358 `define IFENCE_CYCLES                                           36
 359 `define DCACHE_MISS_CYCLES                                      37
 360 `define ICACHE_MISS_CYCLES                                      38
 361 `define FPBUSY_CYCLES                                           39
 362 `define DIVISIONBUSY_CYCLES                             40
 363 `define TOTAL_STALL_CYCLES                                      41
 364 `define PAGEWALK_CYCLES                                         42
 365 `define COREBUS_CYCLES                                          43
 366
 367 ///////////////////////////////////////////////////////////////////////////////////
 368 /*====== Define the slave number of each peripheral=== */
 369 //`ifdef simulate
 370 //      `define Sdram_slave_num                                 0
 371 //      `define Sdram_cfg_slave_num             `Sdram_slave_num
 372 //      `define BootRom_slave_num                       `Sdram_cfg_slave_num+1
 373 //      `define Uart0_slave_num                         `BootRom_slave_num+1
 374 //      `define Uart1_slave_num                         `Uart0_slave_num+1
 375 //      `define Debug_slave_num                         `Uart1_slave_num+1
 376 //      `define Plic_slave_num                          `Debug_slave_num+1
 377 //      `define Qspi0_slave_num          `Plic_slave_num
 378 //      `define Qspi1_slave_num          `Qspi0_slave_num
 379 //      `define Num_Slaves                                      `Qspi1_slave_num
 380 //`else
 381 //      `define Uart0_slave_num           0
 382 //      `define Uart1_slave_num           1
 383 //      `define Qspi0_slave_num           2
 384 //      `define Qspi1_slave_num           3
 385 //      `define I2c0_slave_num                           4
 386 //      `define I2c1_slave_num            5
 387 //      `define Sdram_slave_num           6
 388 //      `define Sdram_cfg_slave_num              7
 389 //      `define Dma_slave_num                            8
 390 //      `define Hyperflash_mem_slave_num  9
 391 //      `define Hyperflash_reg_slave_num  10
 392 //      `define Debug_slave_num                         11
 393 //      `define AxiExp1_slave_num                       12
 394 //      `define GPIO_slave_num                          13
 395 //      `define BootRom_slave_num                       14
 396 //      `define PLIC_slave_num                          15
 397 //      `define TCM_slave_num                           16
 398 //`endif
 399 /*=================================================== */
 400
 401 /*===== Define the base address of each peripheral === */
 402         `define DebugBase               'h00000000
 403         `define DebugEnd                'h000000FF
 404         `define BootRomBase  'h00001000
 405         `define BootRomEnd   'h00010FFF
 406         `define DMABase         'h00011600
 407         `define DMAEnd                  'h000116FF // TODO
 408         `define SDRAMCfgBase    'h00011700
 409         `define SDRAMCfgEnd  'h000117FF // 12 32-bit registers
 410         `define TCMBase         'h00020000 //
 411         `define TCMEnd                  'h00040000 // 128KB
 412   `define VMEBase       'h40000000
 413         `define  VMEEnd  'h4FFFFFFF // 1GB
 414     `ifdef FlexBus_verify
 415         `define FlexBusBase 'h80000000
 416         `define FlexBusEnd 'h8FFFFFFF
 417     `else
 418         `define FlexBusBase 'h50000000
 419         `define FlexBusEnd 'h5FFFFFFF
 420     `endif
 421     `ifdef FlexBus_verify
 422             `define SDRAMMemBase        'h50000000
 423             `define SDRAMMemEnd  'h5FFFFFFF // 1GB
 424     `else
 425             `define SDRAMMemBase        'h80000000
 426             `define SDRAMMemEnd  'h8FFFFFFF // 1GB
 427     `endif
 428         `define AxiExp1Base     'hC0000000
 429         `define AxiExp1End      'hFFFFFFFF
 430 /*=================================================== */
 431 /*== Define the range of bytes per peripheral====
 432 `ifdef simulate
 433         `define MemCRange               'h7FFFFFFF
 434         `define ConfigMRange    'h3000
 435         `define DebugRange              'h44
 436 `else
 437     `define BootRomRange       'hFFF         //4KB for Now
 438          `define GPIORange                       'h8                            //2 registers for GPIO
 439     `define UART0Range         'h38          //8 Registers
 440     `define UART1Range         'h38          //2 registers
 441     `define I2C0Range          'h38          //6 Registers. Adding +2 to just have a backup, if at all it might be required
 442     `define I2C1Range          'h38          //8 registers
 443     `define DMARange           'hFF
 444     `define SDRAMCfgRange      'h58          //12 registers
 445     `define QSPI0CfgRange      'h60          //13 registers
 446     `define QSPI1CfgRange      'h60          //13 registers
 447     `define HyperCfgRange      'h70          //15 registers
 448     `define SDRAMMemRange      'hFFFFFFF     //512 MB
 449     `define HyperMemRange      'hFFFFFFF     //512 MB
 450          `define QSPI0MemRange      'h7FFFFFFF    //2 GB
 451     `define QSPI1MemRange           'h7FFFFFFF    //2 GB
 452     `define AxiExpRange                  'hFFFFFFFF    //512 MB for now!
 453     `define DebugRange         'h44          //16 Registers -- 32 bit
 454 `endif
 455         /*=================================================== */
 456