src/core/decode_opfetch.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
   6
   7 *  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
   8 *  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
   9 *  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
  10
  11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  13 */
  14 package decode_opfetch;
  15         /*============= package imports ========== */
  16         import FIFOF::*;
  17         import TxRx:: *;
  18         import DReg::*;
  19         /* ======================================= */
  20
  21         /* ============== project imports ======= */
  22         import registerfile::*;
  23         import decoder::*;
  24         import defined_types::*;
  25         `include "defined_parameters.bsv"
  26         /* ======================================= */
  27
  28         interface Ifc_decode_opfetch;
  29                 method Action write_rd (Bit#(5)r, Bit#(`Reg_width) d, Operand_type rdtype);
  30                 /* ====================== pipe connections ========= */
  31                 interface RXe#(IF_ID_type) rx_in;
  32                 interface TXe#(ID_IE_type) tx_out;
  33                 /*================================================== */
  34                 `ifdef Debug
  35                         method Bit#(`Reg_width)                 read_debug_igpr (Bit#(5) r);                             // Read a General-Purpose Register
  36                         method Action write_debug_igpr (Bit#(5) r, Bit#(`Reg_width) d);                          // Write a General-Purpose Register
  37                         method Bit#(`Reg_width)                 read_debug_fgpr (Bit#(5) r);                             // Read a General-Purpose Register
  38                         method Action write_debug_fgpr (Bit#(5) r, Bit#(`Reg_width) d);                          // Write a General-Purpose Register
  39                 `endif
  40                 method Action flush();
  41                 method Action trap_from_csr(Tuple2#(Bit#(3),Trap_type) tt);
  42                 method Action misa(Bit#(`Reg_width) val);
  43                 method Action update_eEpoch;
  44                 method Action update_wEpoch;
  45     method Action inferred_xlen(Bit#(2) mxl);
  46         endinterface:Ifc_decode_opfetch
  47
  48                 function Bool isNone(Trap_type trap);
  49                         if(trap matches tagged None)
  50                                 return True;
  51                         else
  52                                 return False;
  53                 endfunction
  54
  55         (*synthesize*)
  56         module mkdecode_opfetch(Ifc_decode_opfetch);
  57                 Reg#(Bit#(`PERFMONITORS)) rg_decode_perfmon<-mkDReg(0);
  58                 Wire#(Tuple2#(Bit#(3),Trap_type)) wr_trap_type<-mkDWire(tuple2(0,tagged None));
  59                 Wire#(Bit#(`Reg_width)) wr_misa<-mkWire();
  60                 Reg#(Bit#(1)) eEpoch <-mkReg(0);
  61                 Reg#(Bit#(1)) wEpoch <-mkReg(0);
  62                 // this is used to ensure that when a trap is
  63                 // taken no other instruction fills the pipe unless wb generates a flush. Stores are avoided using this mechanism
  64                 Reg#(Bool) rg_flush_ahead <-mkReg(False);
  65
  66
  67                 Ifc_registerfile registerfile <-mkregisterfile();
  68                 RX#(IF_ID_type) rx <-mkRX;
  69                 TX#(ID_IE_type) tx <-mkTX;
  70                 /*=================================== Decode and Operand Fetch ======================================================================*/
  71     // This rule decodes the instruction and provides necessary info for the execution units.
  72                 rule rl_operand_fetch(rx.u.notEmpty && tx.u.notFull && !rg_flush_ahead);
  73                         `ifdef verbose
  74                                 $display($time,"\t********** DECODE STAGE FIRING ************ PC: %h EPOCHS: %b Instr-EPOCHS: %b",rx.u.first.program_counter,{eEpoch,wEpoch}, rx.u.first.epochs)  ;
  75                         `endif
  76                         if({eEpoch,wEpoch}!=rx.u.first.epochs)begin
  77                                 `ifdef verbose $display($time,"\tDECODE: PC: %h Dropping Instruction since EPOCSH do not match",rx.u.first.program_counter); `endif
  78                                 rx.u.deq();
  79                         end
  80                         else begin
  81                                 let x = fn_decode(rx.u.first().instruction,rx.u.first.exception, wr_misa, rx.u.first.perfmonitors);
  82                                 let pc=rx.u.first.program_counter;
  83                                 let dest=x.rd;
  84                                 let {debugcause,csr_ex}=wr_trap_type;
  85                                 Bit#(`PERFMONITORS) perfmonitor_incr=x.perf;
  86                         Trap_type exception=x.exception;
  87                 Bool trap_on_wfi = False;
  88                                 if(exception matches tagged None)
  89                                         exception = csr_ex;
  90                                 Bool dnwfi=True;
  91                 if(x.immediate_value[2:0]=='b101 && x.immediate_value[5]==0 && x.funct3==0 && x.inst_type==SYSTEM_INSTR) begin
  92                                         dnwfi=False;
  93                     trap_on_wfi = True;
  94                 end
  95                                 if(exception matches tagged Interrupt .i)
  96                                         dnwfi=True;
  97
  98                 if(trap_on_wfi && dnwfi)
  99                     pc=pc+4;
 100
 101                                 Bit#(`VADDR) nextpc=rx.u.first.nextpc;
 102
 103                                 if(x.inst_type==NOP)begin
 104                                         `ifdef verbose $display($time,"DECODE: NOP Instruction"); `endif
 105                                         rx.u.deq();
 106                                 end
 107                                 else begin
 108                                         Bool choose_rs3=`ifdef spfpu ( `ifdef dpfpu x.inst_type==DFLOATING || `endif x.inst_type==FLOATING) && (rx.u.first.instruction[6:4]=='b100) `else False `endif ;
 109                                         let operands<- registerfile._inputs_from_decode_stage(x.rs1,x.rs1type,x.rs2,x.rs2type,pc,x.immediate_value  `ifdef spfpu ,choose_rs3, x.rs3 `endif );
 110                                         if(dnwfi)begin
 111                                                 Bool e = isNone(exception);
 112                                                 if(!e || x.inst_type==SYSTEM_INSTR)
 113                                                         rg_flush_ahead<=True;
 114                                                 rx.u.deq();
 115                                                 tx.u.enq(ID_IE_type{
 116                                                         rs1:operands.rs1,
 117                                                         rs2:(x.inst_type==MEMORY && (x.mem_access!=Load))?x.immediate_value:operands.rs2,
 118                                                         rs3_imm:`ifdef spfpu (choose_rs3)?operands.rs3: `endif (x.inst_type==MEMORY && x.mem_access!=Load)?operands.rs2:x.immediate_value,
 119                                                         rdtype:x.rdtype,
 120                                                         inst_type:x.inst_type,
 121                                                         destination:x.rd,
 122                                                         program_counter:pc,
 123                                                         exception:exception,
 124                                                         fn:x.fn,
 125                                                         mem_access:x.mem_access,
 126                                                         word32:x.word32,
 127                                                         funct3:x.funct3,
 128                                                         nextpc:rx.u.first.nextpc,
 129                                                         debugcause:debugcause,
 130                                                         perfmonitors:perfmonitor_incr,
 131                                                         prediction:rx.u.first.prediction,
 132                                                         epochs:rx.u.first.epochs,
 133                                                         rs1_type:x.rs1type,
 134                                                         rs2_type:(x.inst_type==MEMORY && (x.mem_access!=Load))?Immediate:x.rs2type,
 135                                                         rs3_type:(x.inst_type==MEMORY && (x.mem_access!=Load))?x.rs2type:`ifdef spfpu choose_rs3?FloatingRF: `endif Immediate,
 136                                                         rs1addr:x.rs1,
 137                                                         rs2addr:x.rs2,
 138                                                         rs3addr:(x.inst_type==MEMORY && (x.mem_access!=Load))?x.rs2:choose_rs3?x.rs3:0
 139                                                         `ifdef simulate ,instruction:rx.u.first.instruction `endif });
 140                                         end
 141                                         else begin
 142                                                 `ifdef verbose $display($time,"\tWaiting for interrupt"); `endif
 143                                         end
 144                                         `ifdef verbose
 145                                         $display($time,"\tDECODE:       Instruction : %h",rx.u.first().instruction," ",fshow(x.inst_type)," FN: %b",x.fn," ",fshow(x.mem_access));
 146                                         $display($time,"\tRs1: %d",x.rs1," ",fshow(x.rs1type));
 147                                         $display($time,"\tRs2: %d",x.rs2," ",fshow(x.rs2type));
 148                                         `ifdef spfpu   $display($time,"\tRs3: %d",x.rs3); `endif
 149                                         $display($time,"\tRd: %d",x.rd," ",fshow(x.rdtype));
 150                                         $display($time,"\tImmediate Value: %h",x.immediate_value);
 151                                         $display($time,"\tException: ",fshow(exception));
 152                                         $display($time,"\t*****************************************************");
 153                                         `endif
 154                                 end
 155                         end
 156            endrule
 157                 /* ============================== method and interface definitions ========================= */
 158                 method tx_out=tx.e;
 159                 method rx_in=rx.e;
 160                 method Action write_rd (Bit#(5)r, Bit#(`Reg_width) d, Operand_type rdtype)=registerfile.write_rd(r,d,rdtype);
 161                 method Action flush();
 162                         `ifdef verbose $display($time,"\tDECODE: Flushing"); `endif
 163                         rg_flush_ahead<=False;
 164                 endmethod
 165                 method Action trap_from_csr(Tuple2#(Bit#(3),Trap_type) tt);
 166                         wr_trap_type<=tt;
 167                 endmethod
 168                 `ifdef Debug
 169                         method read_debug_igpr (Bit#(5) r) = registerfile.read_debug_igpr(r);                            // Read a General-Purpose Register
 170                         method Action write_debug_igpr (Bit#(5) r, Bit#(`Reg_width) d)=registerfile.write_debug_igpr(r,d);                               // Write a General-Purpose Register
 171                         method read_debug_fgpr (Bit#(5) r)=registerfile.read_debug_fgpr(r);                              // Read a General-Purpose Register
 172                         method Action write_debug_fgpr (Bit#(5) r, Bit#(`Reg_width) d)=registerfile.write_debug_fgpr(r,d);                               // Write a General-Purpose Register
 173                 `endif
 174                 method Action misa(Bit#(`Reg_width) val);
 175                         wr_misa<=val;
 176                 endmethod
 177                 method Action update_eEpoch;
 178                         `ifdef verbose $display($time,"\tDECODE: updating eEpoch"); `endif
 179                         eEpoch<=~eEpoch;
 180                 endmethod
 181                 method Action update_wEpoch;
 182                         `ifdef verbose $display($time,"\tDECODE: updating wEpoch"); `endif
 183                         wEpoch<=~wEpoch;
 184                 endmethod
 185     method Action inferred_xlen(Bit#(2) mxl) ;
 186       registerfile.inferred_xlen(mxl);
 187     endmethod
 188 //              method init_complete=registerfile.init_complete;
 189         endmodule
 190 endpackage:decode_opfetch