src/core/defined_types.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
   6
   7 *  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
   8 *  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
   9 *  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
  10
  11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  13
  14 Author Names : Neel Gala, Arjun Menon
  15 Email ID : neelgala@gmail.com
  16
  17 Description :
  18
  19 This files contains all the types and structures that are used in any of the modules.
  20 */
  21 package defined_types;
  22
  23 `include "defined_parameters.bsv"
  24
  25         typedef enum {Load, Store, Atomic, Fence} Access_type deriving (Bits,Eq,FShow);
  26         typedef enum {User=2'd0,Supervisor=2'd1,Machine=2'd3} Privilege_mode deriving (Bits,Eq,FShow);
  27         typedef enum {Idle,Stall,Handling_Request,Handling_Memory_Read, Handling_Memory_Write, Handle_Fence} Cache_State deriving (Bits,Eq,FShow);
  28         typedef enum {Check_vd,Update_vd} Fence_state deriving (Bits,Eq);
  29         typedef enum {AccessFlush,Fence,None} Flush_type deriving (Bits,Eq,FShow);
  30
  31         typedef union tagged{
  32                 Bit#(width) Present;
  33                 Bit#(4) Absent;
  34         } RFType#(numeric type width) deriving(Bits,Eq,FShow);
  35
  36         typedef union tagged{
  37                 void All;
  38                 void None;
  39                 Bit#(TLog#(`PRFDEPTH)) Specific;
  40         }PRFFlush deriving(Bits, Eq, FShow);
  41
  42         typedef union tagged{
  43                 void All;
  44                 void None;
  45                 Tuple2#(Register_type, Bit#(5)) Specific;
  46         }RFFlush deriving(Bits, Eq, FShow);
  47
  48
  49   typedef struct{
  50     Bit#(addr_width) address;
  51   }From_Cpu#(numeric type addr_width) deriving(Bits,Eq);
  52
  53   typedef struct{
  54     Bit#(TMul#(word_size,8)) data_word;
  55     Bit#(1) bus_error;
  56     Bit#(1) misaligned_error;
  57     Bit#(addr_width) address;
  58   }To_Cpu#(numeric type addr_width,numeric type word_size) deriving(Bits,Eq);
  59
  60   typedef struct{
  61     Bit#(addr_width) address;
  62     Bit#(8) burst_length;
  63     Access_type ld_st;
  64          Bit#(3) transfer_size;
  65   }To_Memory#(numeric type addr_width) deriving(Bits,Eq);
  66
  67   typedef struct{
  68     Bit#(TMul#(word_size,8)) data_line;
  69     Bit#(1) bus_error;
  70          Bool last_word;
  71   }From_Memory#(numeric type word_size) deriving(Bits,Eq);
  72
  73   typedef struct{
  74     //Bit#(addr_width) address;
  75     Access_type load_store;
  76     Bit#(TMul#(word_size,8)) data;
  77     Bit#(TLog#(TDiv#(addr_width, 8))) transfer_size; // 0 -8 bits, 1- 16 bits, 2 -32 bits 3 - 64-bits;
  78         `ifdef atomic Bit#(5) atomic_op;`endif
  79         Bool signextend;
  80   }From_Cpu_D#(numeric type addr_width, numeric type word_size) deriving(Bits,Eq,FShow);
  81
  82
  83   typedef struct{
  84     Bit#(TMul#(8,TMul#(word_size,block_size))) line;
  85     Bit#(addr_width) address;
  86     Bit#(TLog#(ways)) replace_block;
  87   } Current_Store#(numeric type ways, numeric type addr_width, numeric type block_size, numeric type word_size) deriving(Bits,Eq);
  88
  89   typedef struct{
  90     Bit#(TMul#(word_size,8)) data_word;
  91     Bit#(1) bus_error;
  92     Bit#(1) misaligned_error;
  93     Bit#(addr_width) address;
  94     Access_type load_store;
  95   }To_Cpu_D#(numeric type addr_width,numeric type word_size) deriving(Bits,Eq);
  96
  97   typedef struct{
  98     Bit#(`PADDR) address;
  99     Bit#(8) burst_length;
 100     Access_type ld_st;
 101     Bit#(TLog#(TDiv#(`VADDR, 8))) transfer_size; // 0 -8 bits, 1- 16 bits, 2 -32 bits 3 - 64-bits;
 102     Bit#(TMul#(`DCACHE_BLOCK_SIZE,TMul#(`DCACHE_WORD_SIZE,8))) data_line;
 103   } To_Memory_Write deriving(Bits,Eq);
 104
 105   typedef struct{
 106     Bit#(TMul#(word_size,8)) data_line;
 107     Bit#(1) bus_error;
 108     Bit#(1) misaligned_error;
 109     Bit#(addr_width) address;
 110   }From_Memory_D#(numeric type addr_width,numeric type word_size, numeric type block_size) deriving(Bits,Eq);
 111
 112
 113 typedef enum{
 114         Taken, Notaken
 115 }Actual_jump deriving (Eq,Bits,FShow); // actual branch condition used in the branch execution unit.
 116
 117
 118 // enum defining the prediction of the branch predictor for the current PC.
 119 typedef enum{
 120         Predicted_taken,Predicted_notaken
 121 }Prediction_type deriving (Eq,Bits,FShow); // output from the branch prediction unit.
 122
 123 // A typedef defining , if the prediction by the branch predictor was correct or wrong.
 124 typedef union tagged{
 125         Bit#(`VADDR) Mispredicted;
 126         Bit#(`VADDR) Correct_prediction;
 127 }Prediction_result deriving (Eq,Bits,FShow); // result of prediuction from the branch execution unit.
 128
 129 typedef struct{
 130         Bit#(addr_width) prog_counter_;
 131   Prediction_type prediction_;
 132   Bool jump;
 133 } Predictor_output#(numeric type addr_width) deriving(Bits, Eq);    // the program counter from the branch prediction unit.
 134
 135 typedef struct{
 136         Bit#(`Reg_width) data_forward;
 137         Bit#(TLog#(`PRFDEPTH)) pid;
 138 }Operand_forwading_type deriving (Bits,Eq);     // the data structure for operand forwarding from any stage
 139
 140 typedef union tagged{
 141         Bit#(`Reg_width) Data;
 142         Bit#(TLog#(`PRFDEPTH)) Pid;
 143 } FromRf deriving (Bits,Eq,FShow);
 144
 145 typedef struct{
 146         Bit#(`Reg_width) rs1;
 147         Bit#(`Reg_width) rs2;
 148   `ifdef spfpu Bit#(`Reg_width) rs3;`endif
 149 } Output_for_operand_fetch deriving (Bits,Eq); // output from the register file to the decode stage
 150
 151 typedef enum {
 152         ALU,MUL,DIV,MEMORY,BRANCH,JAL,JALR `ifdef spfpu ,DFLOATING,FLOATING `endif ,FENCE,FENCEI,SYSTEM_INSTR,NOP
 153 }Instruction_type deriving(Bits, Eq,FShow); // the type of the decoded instruction.
 154
 155 // to distuingish between integer and floating point RF
 156 typedef enum {IntegerRF `ifdef spfpu ,FloatingRF `endif } Register_type deriving(Bits,Eq,FShow);
 157 typedef enum {IntegerRF `ifdef spfpu ,FloatingRF `endif , Immediate, PC} Operand_type deriving(Bits,Eq,FShow);
 158
 159
 160 typedef union tagged{
 161         void None;
 162         Bit#(`Reg_width) Address;
 163         Bit#(`Reg_width) Data;} TriggerType deriving(Bits,Eq,FShow);
 164
 165 typedef struct{
 166         TriggerType ttype;
 167         Bit#(4) matchscheme;} TriggerData deriving(Bits,Eq,FShow);
 168
 169 // the data stucture for the pipeline FIFO between fetch and decode.
 170 typedef struct{
 171         Bit#(`VADDR) program_counter;
 172         Bit#(32) instruction;
 173         Trap_type exception;
 174         Bit#(`VADDR) nextpc;
 175         Bit#(2) prediction;
 176         Bit#(`PERFMONITORS) perfmonitors;
 177         Bit#(2) epochs;
 178 }IF_ID_type deriving (Bits,Eq);
 179
 180 typedef struct{
 181         Bit#(`Reg_width) rs1;
 182         Bit#(`Reg_width) rs2;
 183         Bit#(5) rs1_addr;
 184         Bit#(12) csr_address;
 185         Bit#(3) funct3;
 186         }CSRInputs deriving(Bits,Eq,FShow);
 187
 188 typedef struct{
 189         Instruction_type inst_type;
 190         Operand_type rdtype;
 191         Bit#(`Reg_width) rs1;
 192         Bit#(`Reg_width) rs2;
 193         Bit#(`Reg_width) rs3_imm;
 194         Bit#(5) rs1addr;
 195         Bit#(5) rs2addr;
 196         Bit#(5) rs3addr;
 197         Operand_type rs1_type;
 198         Operand_type rs2_type;
 199         Operand_type rs3_type;
 200         Bit#(`VADDR) program_counter;
 201         Bool word32;
 202         Access_type mem_access;
 203         Bit#(4) fn; // TODO Check is this can suffices for memaccess also
 204         Trap_type exception;
 205         Bit#(5) destination;
 206         Bit#(`VADDR) nextpc;
 207         Bit#(3) funct3;
 208         `ifdef spfpu Bool fcsr_rm; `endif
 209         `ifdef simulate Bit#(32) instruction ;`endif
 210         Bit#(3) debugcause;
 211         Bit#(2) prediction;
 212         Bit#(`PERFMONITORS) perfmonitors;
 213         Bit#(2) epochs;
 214 }ID_IE_type deriving (Bits,Eq);
 215
 216 typedef struct{
 217         Bit#(`Reg_width) address;
 218         Bit#(`Reg_width) memory_data; // data to be written in the memory
 219         Bit#(TLog#(TDiv#(`VADDR, 8))) transfer_size; // 0 -8 bits, 1- 16 bits, 2 -32 bits 3 - 64-bits;
 220         Bit#(1) signextend; // whether the loaded value has to be signextended
 221         Access_type mem_type; // STORE or AMO or LOAD or FENCE
 222         `ifdef atomic Bit#(5) atomic_op;`endif
 223         Bit#(1) epochs;
 224         }Memout deriving(Bits,Eq,FShow);
 225
 226 typedef union tagged{
 227         Arithout RESULT;        // 64+5
 228         Memout MEMORY;          // 64+64+3+1+3+5 = 140
 229         CSRInputs SYSTEM; // 64+64+5+12+3 = 148
 230         void Busy;
 231 } Execution_output deriving(Bits,Eq,FShow);
 232
 233 //typedef struct{
 234 //      Bit#(`Reg_width) result_addr_rs1;
 235 //      Bit#(`Reg_width) data_rs2;
 236 //      Bit#(20) csr_mem;
 237 //} Execution_output deriving(Bits,Eq,FShow);
 238
 239 typedef struct{
 240         Execution_output execresult;
 241         Bit#(`VADDR) program_counter;
 242         Trap_type exception;
 243         Bit#(5) destination;
 244         Operand_type rd_type;
 245         Bit#(TLog#(`PRFDEPTH)) index;
 246         Bit#(4) pid;
 247   `ifdef simulate Bit#(32) instruction ;`endif
 248         Bit#(3) debugcause;
 249         Bit#(`PERFMONITORS) perfmonitors;
 250         Bit#(2) epochs;
 251 }IE_IMEM_type deriving (Bits,Eq);
 252
 253 typedef struct{
 254         Bit#(`Reg_width) aluresult;
 255         Bit#(5) fflags;
 256         } Arithout deriving(Bits,Eq,FShow); // output struct from the alu.
 257
 258 typedef struct{
 259         Bit#(`Reg_width) address;
 260         Bit#(3) transfer_size;
 261         Access_type load_store;
 262         }MemoryResponse deriving(Bits,Eq,FShow);
 263
 264 typedef union tagged{
 265         Arithout RESULT;
 266         CSRInputs SYSTEM;
 267 } WriteBackType deriving(Bits,Eq);
 268
 269 typedef struct{
 270         WriteBackType commit_data;
 271         Bit#(5) destination;
 272         Operand_type rd_type;
 273         Bit#(TLog#(`PRFDEPTH)) index;
 274         Bit#(4) pid;
 275         Bit#(`VADDR) program_counter;
 276         Trap_type exception;
 277   `ifdef simulate Bit#(32) instruction ;`endif
 278         Bit#(3) debugcause;
 279         Bit#(`PERFMONITORS) perfmonitors;
 280         Bit#(2) epochs;
 281 }IMEM_IWB_type deriving(Bits,Eq);
 282
 283 typedef struct {
 284         Bit#(paddr)                      address;
 285         Bit#(TLog#(TDiv#(paddr,8)))  transfer_size;
 286         Bit#(1)                                  u_signed;
 287         Bit#(3)                                         byte_offset;
 288         Bit#(TMul#(8, word_size)) write_data;
 289         Access_type                      ld_st;
 290 } UncachedMemReq#(numeric type paddr, numeric type word_size) deriving(Bits, Eq);
 291
 292 /************************** Interfaces in PLIC ******************************/
 293
 294 interface Ifc_global_interrupt;
 295         method Action irq_frm_gateway(Bool ir);
 296 endinterface
 297
 298 interface Ifc_program_registers#(numeric type addr_width,numeric type word_size);
 299         method ActionValue#(Bit#(TMul#(8,word_size))) prog_reg(UncachedMemReq#(addr_width, word_size) mem_req);
 300 endinterface
 301 /****************************************************************************/
 302
 303 typedef struct {
 304         Bit#(addr_width) pc;
 305         Bit#(addr_width) branch_address;
 306         Bit#(2) state;} Training_data#(numeric type addr_width) deriving (Bits, Eq);
 307
 308 typedef enum {SWAP,ADD,XOR,AND,OR,MINU,MAXU,MIN,MAX} Atomic_funct deriving(Bits,Eq,FShow);
 309
 310 typedef struct{
 311                 Bit#(width) final_result;                                       // the final result for the operation
 312                 Bit#(5) fflags;                                         // indicates if any exception is generated.
 313         }Floating_output#(numeric type width) deriving(Bits,Eq);                                // data structure of the output FIFO.
 314
 315 typedef enum {
 316         Inst_addr_misaligned=0,
 317         Inst_access_fault=1,
 318         Illegal_inst=2,
 319         Breakpoint=3,
 320         Load_addr_misaligned=4,
 321         Load_access_fault=5,
 322         Store_addr_misaligned=6,
 323         Store_access_fault=7,
 324         Ecall_from_user=8,
 325         Ecall_from_supervisor=9,
 326         Ecall_from_machine=11,
 327         Inst_pagefault=12,
 328         Load_pagefault=13,
 329         Store_pagefault=15
 330         `ifdef simulate ,Endsimulation =16 `endif
 331 } Exception_cause deriving (Bits,Eq,FShow);
 332
 333 typedef struct {
 334         Bit#(TSub#(`VADDR,TAdd#(TLog#(`DCACHE_BLOCK_SIZE), TLog#(`DCACHE_WORD_SIZE)))) vtag;
 335         Bit#(`DCACHE_TAG_BITS) ptag;
 336         Bit#(TLog#(`DCACHE_WAYS)) writeblock;
 337         Bit#(1) dirty;
 338         Bit#(1) valid;
 339 } Linebuff_tag deriving (Bits, Eq, FShow);
 340 typedef enum{
 341         /*==== Standard =============== */
 342         User_soft_int=0,
 343         Supervisor_soft_int=1,
 344         Machine_soft_int=3,
 345         User_timer_int=4,
 346         Supervisor_timer_int=5,
 347         Machine_timer_int=7,
 348         User_external_int=8,
 349         Supervisor_external_int=9,
 350         Machine_external_int=11,
 351         /*=============================*/
 352         /*===== Non Standard========= */
 353         DebugInterrupt =12,
 354         DebugResume=13,
 355         DebugReset=14
 356 //      Icache_miss                                                     =12,
 357 //      Icache_cacheable                                        =13,
 358 //      Icache_linereplace                              =14,
 359 //      Icache_tlbmiss                                          =15,
 360 //      Icache_misaligned                               =16,
 361 //      Cond_branch                                                     =17,
 362 //      Cond_branch_taken                               =18,
 363 //      Cond_branch_mispredicted        =19,
 364 //      Taken_branch_mispredicted       =20,
 365 //      Uncond_jumps                                                    =21,
 366 //      Spfpu_inst                                                              =22,
 367 //      Dpfpu_inst                                                              =23,
 368 //      Dcache_tlbmiss                                          =24,
 369 //      Total_loads                                                             =25,
 370 //      Total_stores                                                    =26,
 371 //      Total_atomic                                                    =27,
 372 //      Dcache_load_miss                                        =28,
 373 //      Dcache_store_miss                                       =29,
 374 //      Dcache_atomic_miss                              =30,
 375 //      Dcache_cacheable_load                   =31,
 376 //      Dcache_cacheable_store          =32,
 377 //      Dcache_cacheable_atomic         =33,
 378 //      Dcache_writebacks                                       =34,
 379 //      Dcache_linereplace                              =35,
 380 //      Dcache_misaligned                                       =36,
 381 //      Exceptions_taken                                        =37,
 382 //      Interrupts_taken                                        =38,
 383 //      Muldiv_instructions                             =39,
 384 //      System_instructions                             =40,
 385 //      Usermode_cycles                                         =41,
 386 //      Supervisormode_cycles                   =42,
 387 //      Machinemode_cyles                                       =43,
 388 //      Misprediction_stalls                    =44,
 389 //      Interrupt_stalls                                        =45,
 390 //      Dfence_cycles                                                   =46,
 391 //      Ifence_cycles             =47,
 392 //      Dcache_miss_cycles        =48,
 393 //      Icache_miss_cycles        =49,
 394 //      Fpbusy_cycles             =50,
 395 //      Divisionbusy_cycles                             =51,
 396 //      Total_stall_cycles                              =52,
 397 //      Pagewalk_cycles                                         =53,
 398 //      Corebus_cycles                                          =54
 399 } Interrupt_cause deriving (Bits,Eq,FShow);
 400
 401 typedef union tagged{
 402   Exception_cause Exception;
 403   Interrupt_cause Interrupt;
 404   void None;
 405 } Trap_type deriving(Bits,Eq,FShow);
 406
 407 function String event_name(Bit#(64) eventnum);
 408         case (eventnum)
 409                 'h0000000000000001: return      "ICACHE_MISS                                            ";
 410                 'h0000000000000002: return      "ICACHE_CACHEABLE                                       ";
 411                 'h0000000000000004: return      "ICACHE_LINEREPLACE                             ";
 412                 'h0000000000000008: return      "ICACHE_TLBMISS                                         ";
 413                 'h0000000000000010: return      "ICACHE_MISALIGNED                                      ";
 414                 'h0000000000000020: return      "ICACHE_PREFETCHMISS                            ";
 415                 'h0000000000000040: return      "COND_BRANCH                                            ";
 416                 'h0000000000000080: return      "COND_BRANCH_TAKEN                                      ";
 417                 'h0000000000000100: return      "COND_BRANCH_MISPREDICTED               ";
 418                 'h0000000000000200: return              "TAKEN_BRANCH_MISPREDICTED              ";
 419                 'h0000000000000400: return              "UNCOND_JUMPS                                           ";
 420                 'h0000000000000800: return              "SPFPU_INST                                                     ";
 421                 'h0000000000001000: return              "DPFPU_INST                                                     ";
 422                 'h0000000000002000: return              "DCACHE_TLBMISS                                         ";
 423                 'h0000000000004000: return              "TOTAL_LOADS                                                    ";
 424                 'h0000000000008000: return              "TOTAL_STORES                                           ";
 425                 'h0000000000010000: return              "TOTAL_ATOMIC                                           ";
 426                 'h0000000000020000: return              "DCACHE_LOAD_MISS                                       ";
 427                 'h0000000000040000: return              "DCACHE_STORE_MISS                                      ";
 428                 'h0000000000080000: return              "DCACHE_ATOMIC_MISS                             ";
 429                 'h0000000000100000: return              "DCACHE_CACHEABLE_LOAD                  ";
 430                 'h0000000000200000: return              "DCACHE_CACHEABLE_STORE                 ";
 431                 'h0000000000400000: return              "DCACHE_CACHEABLE_ATOMIC                        ";
 432                 'h0000000000800000: return              "DCACHE_WRITEBACKS                                      ";
 433                 'h0000000001000000: return              "DCACHE_LINEREPLACE                             ";
 434                 'h0000000002000000: return              "DCACHE_MISALIGNED                                      ";
 435                 'h0000000004000000: return              "EXCEPTIONS_TAKEN                                       ";
 436                 'h0000000008000000: return              "INTERRUPTS_TAKEN                                       ";
 437                 'h0000000010000000: return              "MULDIV_INSTRUCTIONS                            ";
 438                 'h0000000020000000: return      "MEMORY_INSTRUCTIONS                            ";
 439                 'h0000000040000000: return      "EXEC_FLUSHES                                           ";
 440                 'h0000000080000000: return      "WB_FLUSHES                                                     ";
 441                 default: return "NO EVENT";
 442         endcase
 443 endfunction
 444
 445 /****************************** MMU TYPES *******************************/
 446
 447 typedef struct {
 448         bit                     mprv;
 449         bit                     sum;
 450         bit                     mxr;
 451         Privilege_mode mpp;
 452         Privilege_mode prv;
 453 } Chmod deriving(Bits, Eq);
 454
 455 typedef struct {
 456         bit v;                                  //valid
 457         bit r;                                  //allow reads
 458         bit w;                                  //allow writes
 459         bit x;                                  //allow execute(instruction read)
 460         bit u;                                  //allow supervisor
 461         bit g;                                  //global page
 462         bit a;                                  //accessed already
 463         bit d;                                  //dirty
 464 } TLB_permissions deriving(Bits, Eq, FShow);
 465
 466 typedef struct {
 467         Bit#(TSub#(paddr,page_size)) ppn;
 468         TLB_permissions                                 tlb_perm;
 469         Bit#(asid_width)                                                asid;
 470         Bit#(2)                                                                         levels;
 471 } To_TLB#(numeric type paddr, numeric type page_size, numeric type asid_width) deriving(Bits,Eq);
 472
 473 typedef struct {
 474         Bit#(data_width) vaddr;
 475         Access_type  ld_st_atomic;
 476 } DTLB_access#(numeric type data_width) deriving(Bits, Eq);
 477
 478 typedef enum {
 479                 PTW_ready, Handling_PTW, Wait_for_memory, PTW_done, Send_to_memory} PTW_state deriving(Bits, Eq);
 480
 481 typedef enum {
 482                 Load, Store, Execution} Translation_type deriving(Bits, Eq);
 483
 484 typedef struct {
 485         Translation_type        page_type;
 486         Bit#(TSub#(vaddr_width,page_offset))    vpn;
 487 } Request_PPN_PTW#(numeric type vaddr_width, numeric type page_offset) deriving (Bits,Eq);
 488
 489 typedef struct {
 490         Translation_type        page_type;
 491         To_TLB#(paddr_width,page_offset,asid_width)     tlb_packet;
 492 } Response_PPN_TLB#(numeric type paddr_width, numeric type page_offset, numeric type asid_width) deriving (Bits,Eq);
 493
 494 typedef struct {
 495         Bool ptwdone;
 496         Translation_type        page_type;
 497         Bit#(data_width)        address;
 498 } Request_PTE_memory#(numeric type data_width) deriving (Bits,Eq);
 499
 500 typedef struct {
 501         Trap_type exception;
 502         Bit#(data_width) address;
 503         Bool                                             cacheable;
 504 } From_TLB#(numeric type data_width) deriving (Bits, Eq);
 505
 506 typedef struct {
 507         Bit#(vaddr_width) rs1;
 508         Bit#(vaddr_width) rs2;
 509 } Fence_VMA_type#(numeric type vaddr_width) deriving (Bits, Eq);
 510
 511 typedef enum {
 512         Store_pf, Load_pf, Instruction_pf, None} Pf_exception_type deriving (Bits, Eq);
 513 /*=============================================================================== */
 514
 515 /* =============================== Debug related types ========================== */
 516 typedef enum {CPU_CONTINUE,CPU_STOPPED} CPU_State deriving(Bits,Eq,FShow);
 517 typedef enum {
 518               GDB_INTERRUPT,
 519               GDB_HUP,
 520               GDB_INT,
 521               GDB_QUIT,
 522               GDB_ILL,
 523               GDB_BREAK = 5,
 524               CPU_BUSY
 525    } GdbStopCondition
 526 deriving (Bits ,Eq, FShow);
 527
 528 /*======= AXI4 master/slave numbers ======*/
 529 typedef 0 Sdram_slave_num;
 530 typedef  TAdd#(Sdram_slave_num   ,`ifdef SDRAM          1 `else 0 `endif )              Sdram_cfg_slave_num;
 531 typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM        1 `else 0 `endif )              BootRom_slave_num       ;
 532 typedef TAdd#(BootRom_slave_num  ,`ifdef Debug          1 `else 0 `endif )              Debug_slave_num ;
 533 typedef  TAdd#(Debug_slave_num   , `ifdef TCMemory      1 `else 0 `endif )              TCM_slave_num;
 534 typedef  TAdd#(TCM_slave_num     ,`ifdef DMA                    1 `else 0 `endif )      Dma_slave_num;
 535 typedef  TAdd#(Dma_slave_num      ,1 )          SlowPeripheral_slave_num;
 536 typedef  TAdd#(SlowPeripheral_slave_num,`ifdef VME      1 `else 0 `endif )       VME_slave_num;
 537 typedef  TAdd#(VME_slave_num,`ifdef FlexBus     1 `else 0 `endif )              FlexBus_slave_num;
 538 typedef TAdd#(FlexBus_slave_num,1)                                               Num_Slaves;
 539 typedef 0 Dmem_master_num;
 540 typedef 1 Imem_master_num;
 541 typedef TAdd#(Imem_master_num , `ifdef Debug 1 `else 0 `endif ) Debug_master_num;
 542 typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif ) DMA_master_num;
 543 typedef TAdd#(DMA_master_num,1) Num_Masters;
 544
 545 /*=============================================================================== */
 546 /*====== AXI4 Lite slave declarations =======*/
 547 typedef  0      SlowMaster;
 548 typedef 0       Uart0_slave_num ;
 549 typedef  TAdd#(Uart0_slave_num          ,`ifdef UART1           1 `else 0 `endif )              Uart1_slave_num ;
 550 typedef  TAdd#(Uart1_slave_num          ,`ifdef CLINT           1 `else 0 `endif )              CLINT_slave_num;
 551 typedef  TAdd#(CLINT_slave_num          ,`ifdef PLIC            1 `else 0 `endif )              Plic_slave_num          ;
 552 typedef  TAdd#(Plic_slave_num                   ,`ifdef PLIC            1 `else 0 `endif )              GPIO_slave_num   ;
 553 typedef  TAdd#(GPIO_slave_num                   ,`ifdef I2C0            1 `else 0 `endif )              I2c0_slave_num   ;
 554 typedef  TAdd#(I2c0_slave_num                   ,`ifdef I2C1            1 `else 0 `endif )              I2c1_slave_num   ;
 555 typedef  TAdd#(I2c1_slave_num                   ,`ifdef QSPI0           1 `else 0 `endif )              Qspi0_slave_num   ;
 556 typedef  TAdd#(Qspi0_slave_num          ,`ifdef QSPI1           1 `else 0 `endif )              Qspi1_slave_num   ;
 557 typedef  TAdd#(Qspi1_slave_num          ,`ifdef AXIEXP          1 `else 0 `endif )              AxiExp1_slave_num;
 558 typedef  TAdd#(AxiExp1_slave_num  ,`ifdef PWM_AXI4Lite 1 `else 0 `endif ) Pwm_slave_num;
 559 typedef TAdd#(Pwm_slave_num,1)                                                                  Num_Slow_Slaves                 ;
 560 /*===========================================*/
 561
 562 endpackage