src/core/fpu/fpu_fclass.bsv

   1 /*
   2 Authors     : Vinod.G, Renuka Venkat
   3 Email       : g.vinod1993@gmail.com
   4 Last Update : 27th November 2017
   5 See License for More Details
   6 Description:
   7 This module examines the floating point input and outputs the class of floating point number. The corresponding bit of the output register is set according to the class of instructions given by the table below,
   8                            bit                  Class
   9                             0                   Negative Infinity
  10                             1                   Negative Normal Number
  11                             2                   Negative Subnormal Number
  12                             3                   Negative Zero
  13                             4                   Positive Zero
  14                             5                   Positive Subnormal Number
  15                             6                   Positive Normal Number
  16                             7                   Positive Infinity
  17                             8                   Signaling NaN
  18                             9                   Quiet NaN
  19
  20 The module examines and finds the class as follows
  21 Sign    Exponent (e)    Fraction (f)    Value
  22 0       00⋯00           00⋯00               +0
  23
  24 0       00⋯00           00⋯01        Positive Denormalized Real
  25                           ⋮                   0.f × 2(−b+1)
  26                           11⋯11
  27
  28 0       00⋯01             XX⋯XX            Positive Normalized Real
  29            ⋮                                   1.f × 2(e−b)
  30         11⋯10
  31
  32 0       11⋯11           00⋯00               +∞
  33
  34 0       11⋯11           00⋯01        SNaN
  35                           ⋮
  36                           01⋯11
  37
  38 0       11⋯11           1X⋯XX              QNaN
  39
  40
  41 1       00⋯00           00⋯00              −0
  42
  43 1       00⋯00           00⋯01        Negative Denormalized Real
  44                           ⋮                   −0.f × 2(−b+1)
  45                           11⋯11
  46
  47 1       00⋯01             XX⋯XX            Negative Normalized Real
  48         ⋮                                      −1.f × 2(e−b)
  49         11⋯10
  50
  51 1       11⋯11           00⋯00              −∞
  52
  53 1       11⋯11           00⋯01        SNaN
  54                           ⋮
  55                           01⋯11
  56
  57 1       11⋯11           1X⋯XX              QNaN
  58
  59 */
  60
  61
  62 package fpu_fclass;
  63
  64 import defined_types::*;
  65 `include "defined_parameters.bsv"
  66
  67 interface Ifc_fpu_fclass#(numeric type fpinp, numeric type fpman, numeric type fpexp);
  68         method ActionValue#(Floating_output#(fpinp)) _start(Bit#(1) sign1,Bit#(fpman)mantissa,Bit#(fpexp)exponent, Bit#(5) flags);
  69 endinterface
  70
  71 `ifdef fpu_hierarchical
  72 interface Ifc_fpu_fclass32;
  73         method ActionValue#(Floating_output#(32)) _start(Bit#(1) sign1,Bit#(23)mantissa,Bit#(8)exponent, Bit#(5) flags);
  74 endinterface
  75
  76 interface Ifc_fpu_fclass64;
  77         method ActionValue#(Floating_output#(64)) _start(Bit#(1) sign1,Bit#(52)mantissa,Bit#(11)exponent, Bit#(5) flags);
  78 endinterface
  79 `endif
  80
  81 module mkfpu_fclass(Ifc_fpu_fclass#(fpinp,fpman,fpexp))
  82         provisos (
  83                 Add#(TAdd#(fpexp,fpman),1,fpinp),                       //Defining fpinp to be fpexp + fpman + 1
  84                 Add#(fpexp,2,fpexp2),
  85     Add#(a__, 10, fpinp)
  86                  );
  87
  88         let fPINP  = valueOf(fpinp);
  89         let fPMAN  = valueOf(fpman);
  90         let fPEXP  = valueOf(fpexp);
  91
  92         method ActionValue#(Floating_output#(fpinp)) _start(Bit#(1) sign1,Bit#(fpman)mantissa,Bit#(fpexp)exponent, Bit#(5) flags);
  93
  94                 Bit#(10) result_fclass;
  95         Bool sbit = (sign1==1);
  96         Bool inf  = (flags[1]==1);
  97         Bool normal = (flags == '0);
  98         Bool subnormal = (flags[4] == 1);
  99         Bool zero    = (flags[3] == 1);
 100                 if(sbit && inf)  //negtive infinity
 101                 begin
 102                 result_fclass = 'd1;
 103                 end
 104
 105                 else if(sbit && normal)  //negative normal
 106                 begin
 107                 result_fclass = 'd2;
 108             end
 109
 110                 else if(sbit && subnormal) //negative subnormal
 111                 begin
 112                 result_fclass = 'd4;
 113                 end
 114
 115                 else if(sbit && zero)  //-0
 116                 begin
 117                 result_fclass = 'd8;
 118                 end
 119
 120                 else if(!sbit && zero) // +0
 121                 begin
 122                 result_fclass = 'd16;
 123                 end
 124
 125                 else if( !sbit && subnormal) //positive subnormal
 126                 begin
 127                 result_fclass = 'd32;
 128             end
 129
 130                 else if(!sbit && normal)  //positive normal
 131                 begin
 132                 result_fclass = 'd64;
 133                 end
 134
 135                 else if(!sbit && inf) //positive infinity
 136                 begin
 137                 result_fclass = 'd128;
 138                 end
 139
 140                 else if (flags[0]==1) //Signaling NaN
 141                 begin
 142                 result_fclass = 'd256;
 143                 end
 144
 145                 else  //quiet NaN
 146                 begin
 147                   result_fclass = 'd512;
 148                 end
 149
 150
 151
 152                 return Floating_output {
 153                         final_result : zeroExtend(result_fclass),
 154                         fflags: 5'b0 };
 155         endmethod
 156 endmodule
 157
 158 `ifdef fpu_hierarchical
 159 (*synthesize*)
 160 module mkfpu_fclass32(Ifc_fpu_fclass32);
 161     Ifc_fpu_fclass#(32,23,8) uut <- mkfpu_fclass();
 162         method ActionValue#(Floating_output#(32)) _start(Bit#(1) sign1,Bit#(23)mantissa,Bit#(8)exponent, Bit#(5) flags);
 163         let x <- uut._start(sign1,mantissa,exponent,flags);
 164         return x;
 165     endmethod
 166 endmodule
 167
 168 (*synthesize*)
 169 module mkfpu_fclass64(Ifc_fpu_fclass64);
 170     Ifc_fpu_fclass#(64,52,11) uut <- mkfpu_fclass();
 171         method ActionValue#(Floating_output#(64)) _start(Bit#(1) sign1,Bit#(52)mantissa,Bit#(11)exponent, Bit#(5) flags);
 172         let x <- uut._start(sign1,mantissa,exponent,flags);
 173         return x;
 174     endmethod
 175 endmodule
 176 `endif
 177
 178 // (*synthesize*)
 179 //      module mkTb_fpu_fclass();
 180 //      Ifc_fpu_fclass#(32,23,8) inst_fpu_fclass <- mkfpu_fclass();
 181 //      Reg#(Bit#(32)) rg_clock <- mkReg(0);
 182 //      Reg#(Bit#(32)) rg_operand1<-mkReg('h7f8ff000); //positive normal set 6
 183
 184 //      rule get_input(rg_clock == 0);
 185 //              inst_fpu_fclass._start(rg_operand1);
 186 //              rg_clock <= rg_clock + 1;
 187 //      endrule
 188
 189 //      rule get_output;
 190 //              let lv_result = inst_fpu_fclass.result_();
 191 //              `ifdef verbose $display("Result is: %h",lv_result.final_result); `endif
 192 //              $finish(0);
 193 //      endrule
 194
 195 // endmodule
 196
 197 endpackage