src/core/fpu/integermultiplier.bsv

   1 /*
   2 Copyright (c) 2013-2016, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
   6
   7 *  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
   8 *  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
   9 *  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
  10
  11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  13
  14 Module Name     : Sequential Integer Multiplier Unit
  15 Author's Name   : Neel Gala, Vinod.G
  16 e-mail id       : neelgala@gmail.com, g.vinod1993@gmail.com
  17 Last updated on : 5th August 2016
  18
  19 */
  20
  21 package integermultiplier;
  22   import DReg::*;
  23   interface Ifc_integermultiplier#(numeric type regwidth, numeric type loop);
  24     method ActionValue#(Maybe#(Bit#(TMul#(2,regwidth)))) _start(Bit#(regwidth) inp1, Bit#(regwidth) inp2); //_div_name 00 : DIV/REM 01: DIVU/REMU
  25   endinterface
  26   //(*synthesize*)
  27   module mkintegermultiplier(Ifc_integermultiplier#(regwidth,loop))
  28      provisos ( Add#(regwidth,1,regwidth1),
  29                 Add#(regwidth,regwidth,regwidth_twice),
  30                 Add#(1,TMul#(2,regwidth),regwidth_twice1),
  31                 Add#(1,TLog#(regwidth),regwidth_log1),
  32                 //per request of bsc
  33                 Add#(regwidth1,regwidth,regwidth_twice1)
  34               );
  35
  36     Reg#(Bit#(regwidth_twice1)) partial_prod <-mkReg(0);
  37     Reg#(Bit#(regwidth_log1)) rg_state_counter <-mkDReg(0);//Register for state machine counter
  38     let rEGWIDTH = valueOf(regwidth);
  39     let lOOP = valueOf(loop);
  40
  41     method ActionValue#(Maybe#(Bit#(regwidth_twice))) _start(Bit#(regwidth) inp1, Bit#(regwidth) inp2);
  42         `ifdef verbose $display("Taken inputs in multiplier. rs1: %h rs2: %h",inp1,inp2); `endif
  43       `ifdef verbose $display("Register State Counter %h", rg_state_counter);`endif
  44       `ifdef verbose $display("partial_prod %h", partial_prod);`endif
  45       if(rg_state_counter==0)begin
  46              partial_prod<=zeroExtend(inp2);
  47          rg_state_counter<=rg_state_counter+1;
  48          return tagged Invalid;
  49       end
  50       else begin
  51               Bit#(regwidth) temp=(partial_prod[lOOP-1:0])*inp1[rEGWIDTH-1:0];
  52               Bit#(regwidth1) accum=partial_prod[2*rEGWIDTH:rEGWIDTH]+zeroExtend(temp);
  53           Bit#(regwidth) partial_prod_temp = partial_prod[rEGWIDTH-1:0];
  54               Bit#(regwidth_twice1) temp1 ={accum,partial_prod_temp}>>lOOP;
  55               `ifdef verbose $display("multiplication. Partial :%h Counter: %d",temp1,rg_state_counter);`endif
  56               if(rg_state_counter==(fromInteger(rEGWIDTH)/fromInteger(lOOP)))begin
  57                  rg_state_counter<=0;
  58                  return tagged Valid temp1[2*rEGWIDTH-1:0];
  59               end
  60               else begin
  61                  partial_prod<=temp1;
  62                  rg_state_counter<=rg_state_counter+1;
  63                  return tagged Invalid;
  64               end
  65           end
  66       endmethod
  67   endmodule
  68
  69   module mkTb(Empty);
  70    Ifc_integermultiplier#(8,4) mul <- mkintegermultiplier();
  71    Reg#(Bit#(8)) inp1 <- mkReg(8'b1100);
  72    Reg#(Bit#(8)) inp2 <- mkReg(8'b1010);
  73
  74    rule give_inputs;
  75    let x <- mul._start(inp1,inp2);
  76    if(x matches tagged Valid .res) begin
  77        `ifdef verbose $display("Output is %b",res);`endif
  78        $finish(0);
  79    end
  80    endrule
  81
  82    endmodule
  83 endpackage