src/core/mem_config1.bsv

   1 package mem_config1;
   2         import BRAMCore::*;
   3         import defined_types::*;
   4         `include "core_parameters.bsv"
   5         import Assert::*;
   6         import DReg::*;
   7         interface Ifc_dcache_data;
   8                 method Action read_request(Bit#(TLog#(`DCACHE_SETS)) address);
   9                 method Bit#(TMul#(TMul#(8,`DCACHE_WORD_SIZE),`DCACHE_BLOCK_SIZE)) read_response;
  10                 method Action write_request(Bit#(TMul#(`DCACHE_WORD_SIZE,`DCACHE_BLOCK_SIZE))we, Bit#(TLog#(`DCACHE_SETS)) address, Bit#(TMul#(TMul#(8,`DCACHE_WORD_SIZE),`DCACHE_BLOCK_SIZE)) data);
  11         endinterface
  12
  13
  14         module mkdcache_data(Ifc_dcache_data);
  15                 BRAM_DUAL_PORT_BE#(Bit#(TLog#(`DCACHE_SETS)),Bit#(128),16) dataa <-mkBRAMCore2BE(`DCACHE_SETS,False);
  16                 BRAM_DUAL_PORT_BE#(Bit#(TLog#(`DCACHE_SETS)),Bit#(128),16) datab <-mkBRAMCore2BE(`DCACHE_SETS,False);
  17
  18                 Wire#(Bit#(TLog#(`DCACHE_SETS))) read_address <-mkWire();
  19                 Wire#(Bit#(TLog#(`DCACHE_SETS))) write_address<-mkWire();
  20                 let set_bits=valueOf(TLog#(`DCACHE_SETS));                      // number of bits to select a set from the cache. =
  21
  22
  23                 rule print_address;
  24                         `ifdef verbose $display("\tASSERT: DATA read_address: %d write_address: %d",read_address,write_address); `endif
  25                         dynamicAssert(read_address!=write_address,"ASSERT: DATA read and write address are the same");
  26                 endrule
  27
  28
  29                 method Action read_request(Bit#(TLog#(`DCACHE_SETS)) address);
  30                         dataa.a.put(0,address,?);
  31                         datab.a.put(0,address,?);
  32                         read_address<=address[set_bits-1:0];
  33                 endmethod
  34                 method Bit#(TMul#(TMul#(8,`DCACHE_WORD_SIZE),`DCACHE_BLOCK_SIZE)) read_response;
  35                         return {dataa.a.read,datab.a.read};
  36                 endmethod
  37                 method Action write_request(Bit#(TMul#(`DCACHE_WORD_SIZE,`DCACHE_BLOCK_SIZE))we, Bit#(TLog#(`DCACHE_SETS)) address, Bit#(TMul#(TMul#(8,`DCACHE_WORD_SIZE),`DCACHE_BLOCK_SIZE)) data);
  38                         dataa.b.put(we[31:16],address,data[255:128]);
  39                         datab.b.put(we[15:0],address,data[127:0]);
  40                         if(we!=0)
  41                                 write_address<=address[set_bits-1:0];
  42                 endmethod
  43         endmodule
  44
  45         interface Ifc_dcache_tag;
  46                 method Action read_request(Bit#(TLog#(`DCACHE_SETS)) address);
  47                 method Bit#(TAdd#(2,`DCACHE_TAG_BITS)) read_response;
  48                 method Action write_request(Bool we, Bit#(TLog#(`DCACHE_SETS)) address, Bit#(TAdd#(2,`DCACHE_TAG_BITS)) data);
  49         endinterface
  50
  51         module mkdcache_tag(Ifc_dcache_tag);
  52                 let byte_bits=valueOf(TLog#(`DCACHE_WORD_SIZE));        // number of bits to select a byte within a word. = 2
  53                 let word_bits=valueOf(TLog#(`DCACHE_BLOCK_SIZE));       // number of bits to select a word within a block. = 4
  54                 let set_bits=valueOf(TLog#(`DCACHE_SETS));                      // number of bits to select a set from the cache. =
  55
  56                 BRAM_DUAL_PORT#(Bit#(TLog#(TDiv#(`DCACHE_SETS,2))),Bit#(TAdd#(`DCACHE_TAG_BITS,2))) taga<-mkBRAMCore2(`DCACHE_SETS/2,False) ;
  57                 BRAM_DUAL_PORT#(Bit#(TLog#(TDiv#(`DCACHE_SETS,2))),Bit#(TAdd#(`DCACHE_TAG_BITS,2))) tagb<-mkBRAMCore2(`DCACHE_SETS/2,False) ;
  58                 Reg#(Bit#(TLog#(`DCACHE_SETS))) rg_addr <-mkReg(0);
  59
  60                 Wire#(Bit#(TLog#(`DCACHE_SETS))) read_address <-mkWire();
  61                 Wire#(Bit#(TLog#(`DCACHE_SETS))) write_address<-mkWire();
  62
  63                 rule print_address;
  64                         `ifdef verbose $display("\tASSERT: read_address: %d write_address: %d",read_address,write_address); `endif
  65                         dynamicAssert(read_address!=write_address,"ASSERT: Tag read and write address are the same");
  66                 endrule
  67
  68
  69                 method Action read_request(Bit#(TLog#(`DCACHE_SETS)) address);
  70                         if(address[set_bits-1]==1)
  71                                 tagb.a.put(False,address[set_bits-2:0],?);
  72                         else
  73                                 taga.a.put(False,address[set_bits-2:0],?);
  74                         rg_addr<=address;
  75                         read_address<=address[set_bits-1:0];
  76                 endmethod
  77                 method Bit#(TAdd#(2,`DCACHE_TAG_BITS)) read_response;
  78                         if(rg_addr[set_bits-1]==1)
  79                                 return tagb.a.read;
  80                         else
  81                                 return taga.a.read;
  82                 endmethod
  83                 method Action write_request(Bool we, Bit#(TLog#(`DCACHE_SETS)) address, Bit#(TAdd#(2,`DCACHE_TAG_BITS)) data);
  84                         if(address[set_bits-1]==1)
  85                                 tagb.b.put(we,address[set_bits-2:0],data);
  86                         else
  87                                 taga.b.put(we,address[set_bits-2:0],data);
  88                         if(we)
  89                                 write_address<=address[set_bits-1:0];
  90                 endmethod
  91         endmodule
  92 endpackage