src/testbench/Memory_AXI4.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
   6
   7 *  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
   8 *  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
   9 *  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
  10
  11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  13 */
  14
  15 package Memory_AXI4;
  16         /*====== Porject imports ====*/
  17         import defined_types::*;
  18         `include "core_parameters.bsv"
  19         import Semi_FIFOF        :: *;
  20         import AXI4_Types   :: *;
  21         import AXI4_Fabric  :: *;
  22         import axi_addr_generator::*;
  23         /*==== Package imports ======*/
  24         import BRAMCore :: *;
  25         import DReg::*;
  26         import BUtils::*;
  27         /*============================*/
  28
  29         interface Memory_IFC#(numeric type base_address, numeric type mem_size);
  30                 interface AXI4_Slave_IFC#(`PADDR,`Reg_width,`USERSPACE) axi_slave;
  31         endinterface
  32         typedef enum{Idle,HandleBurst} Mem_state deriving(Bits,Eq);
  33         module mkMemory #(parameter String mem_init_file1 `ifdef RV64 , parameter String mem_init_file2 `endif  ,parameter String module_name) (Memory_IFC#(base_address,mem_size));
  34
  35                 BRAM_DUAL_PORT_BE#(Bit#(TSub#(mem_size,2)),Bit#(32),4) dmemMSB <- mkBRAMCore2BELoad(valueOf(TExp#(TSub#(mem_size,2))),False,mem_init_file1,False);
  36                 BRAM_DUAL_PORT_BE#(Bit#(TSub#(mem_size,2)),Bit#(32),4) dmemLSB <- mkBRAMCore2BELoad(valueOf(TExp#(TSub#(mem_size,2))),False,mem_init_file2,False);
  37
  38                 AXI4_Slave_Xactor_IFC #(`PADDR, `Reg_width, `USERSPACE)  s_xactor <- mkAXI4_Slave_Xactor;
  39
  40                 Reg#(Mem_state) rd_state <-mkReg(Idle);
  41                 Reg#(Mem_state) wr_state <-mkReg(Idle);
  42                 Reg#(Bit#(8)) rg_readburst_counter<-mkReg(0);
  43                 Reg#(AXI4_Rd_Addr       #(`PADDR,`USERSPACE)) rg_read_packet <-mkReg(?);                                                                                                                   // hold the read packet during bursts
  44                 Reg#(AXI4_Wr_Addr       #(`PADDR,`USERSPACE)) rg_write_packet<-mkReg(?); // hold the write packer during bursts
  45
  46                 rule rl_wr_respond(wr_state==Idle);
  47               let aw <- pop_o (s_xactor.o_wr_addr);
  48               let w  <- pop_o (s_xactor.o_wr_data);
  49                         Bit#(TSub#(mem_size,2)) index_address=(aw.awaddr-fromInteger(valueOf(base_address)))[valueOf(mem_size)-1:`byte_offset+1];
  50                         dmemLSB.b.put(w.wstrb[3:0],index_address,truncate(w.wdata));
  51                         dmemMSB.b.put(w.wstrb[7:4],index_address,truncateLSB(w.wdata));
  52                    let b = AXI4_Wr_Resp {bresp: AXI4_OKAY, buser: aw.awuser, bid:aw.awid};
  53                         if(aw.awlen!=0) begin
  54                                 wr_state<=HandleBurst;
  55                                 let new_address=burst_address_generator(aw.awlen,aw.awsize,aw.awburst,aw.awaddr);
  56                                 aw.awaddr=new_address;
  57                                 rg_write_packet<=aw;
  58                         end
  59                         else
  60                         s_xactor.i_wr_resp.enq (b);
  61                         `ifdef verbose $display($time,"\t",module_name,":\t Recieved Write Request for Address: %h data: %h strb: %b awlen: %d",aw.awaddr,w.wdata,w.wstrb,aw.awlen);  `endif
  62                 endrule
  63
  64                 rule rl_wr_burst_response(wr_state==HandleBurst);
  65               let w  <- pop_o (s_xactor.o_wr_data);
  66                    let b = AXI4_Wr_Resp {bresp: AXI4_OKAY, buser: rg_write_packet.awuser, bid:rg_write_packet.awid};
  67                         if(w.wlast)begin
  68                                 wr_state<=Idle;
  69                                 s_xactor.i_wr_resp.enq (b);
  70                         end
  71                         Bit#(TSub#(mem_size,2)) index_address=(rg_write_packet.awaddr-fromInteger(valueOf(base_address)))[valueOf(mem_size)-1:`byte_offset+1];
  72                         dmemLSB.b.put(w.wstrb[3:0],index_address,truncate(w.wdata));
  73                         dmemMSB.b.put(w.wstrb[7:4],index_address,truncateLSB(w.wdata));
  74                         let new_address=burst_address_generator(rg_write_packet.awlen,rg_write_packet.awsize,rg_write_packet.awburst,rg_write_packet.awaddr);
  75                         rg_write_packet.awaddr<=new_address;
  76                         `ifdef verbose $display($time,"\t",module_name,":\t BURST Write Request for Address: %h data: %h strb: %b awlen: %d",rg_write_packet.awaddr,w.wdata,w.wstrb,rg_write_packet.awlen);  `endif
  77                 endrule
  78
  79                 rule rl_rd_request(rd_state==Idle);
  80                         let ar<- pop_o(s_xactor.o_rd_addr);
  81                         rg_read_packet<=ar;
  82                         Bit#(TSub#(mem_size,2)) index_address=(ar.araddr-fromInteger(valueOf(base_address)))[valueOf(mem_size)-1:`byte_offset+1];
  83                         dmemLSB.a.put(0,index_address,?);
  84                         dmemMSB.a.put(0,index_address,?);
  85                         rd_state<=HandleBurst;
  86                         `ifdef verbose $display($time,"\t",module_name,"\t Recieved Read Request for Address: %h Index Address: %h",ar.araddr,index_address);  `endif
  87                 endrule
  88
  89                 rule rl_rd_response(rd_state==HandleBurst);
  90                    Bit#(`Reg_width) data0 = {dmemMSB.a.read(),dmemLSB.a.read()};
  91               AXI4_Rd_Data#(`Reg_width,`USERSPACE) r = AXI4_Rd_Data {rresp: AXI4_OKAY, rdata: data0 ,rlast:rg_readburst_counter==rg_read_packet.arlen, ruser: 0, rid:rg_read_packet.arid};
  92                         let transfer_size=rg_read_packet.arsize;
  93                         let address=rg_read_packet.araddr;
  94                         if(transfer_size==2)begin // 32 bit
  95                                 if(address[2:0]==0)
  96                                         r.rdata=duplicate(data0[31:0]);
  97                                 else
  98                                         r.rdata=duplicate(data0[63:32]);
  99                         end
 100               else if (transfer_size=='d1)begin // half_word
 101                                 if(address[2:0] ==0)
 102                                         r.rdata = duplicate(data0[15:0]);
 103                                 else if(address[2:0] ==2)
 104                                         r.rdata = duplicate(data0[31:16]);
 105                                 else if(address[2:0] ==4)
 106                                         r.rdata = duplicate(data0[47:32]);
 107                                 else if(address[2:0] ==6)
 108                                         r.rdata = duplicate(data0[63:48]);
 109               end
 110               else if (transfer_size=='d0) begin// one byte
 111                                 if(address[2:0] ==0)
 112                           r.rdata = duplicate(data0[7:0]);
 113                         else if(address[2:0] ==1)
 114                           r.rdata = duplicate(data0[15:8]);
 115                         else if(address[2:0] ==2)
 116                           r.rdata = duplicate(data0[23:16]);
 117                         else if(address[2:0] ==3)
 118                           r.rdata = duplicate(data0[31:24]);
 119                         else if(address[2:0] ==4)
 120                                         r.rdata = duplicate(data0[39:32]);
 121                         else if(address[2:0] ==5)
 122                                         r.rdata = duplicate(data0[47:40]);
 123                         else if(address[2:0] ==6)
 124                                         r.rdata = duplicate(data0[55:48]);
 125                         else if(address[2:0] ==7)
 126                                         r.rdata = duplicate(data0[63:56]);
 127               end
 128               s_xactor.i_rd_data.enq(r);
 129                         address=burst_address_generator(rg_read_packet.arlen, rg_read_packet.arsize, rg_read_packet.arburst,rg_read_packet.araddr);
 130                         Bit#(TSub#(mem_size,2)) index_address=(address-fromInteger(valueOf(base_address)))[valueOf(mem_size)-1:`byte_offset+1];
 131                         if(rg_readburst_counter==rg_read_packet.arlen)begin
 132                                 rg_readburst_counter<=0;
 133                                 rd_state<=Idle;
 134                         end
 135                         else begin
 136                                 dmemLSB.a.put(0,index_address,?);
 137                                 dmemMSB.a.put(0,index_address,?);
 138                                 rg_readburst_counter<=rg_readburst_counter+1;
 139                         end
 140                         rg_read_packet.araddr<=address;
 141                         Bit#(64) new_data=r.rdata;
 142                         `ifdef verbose $display($time,"\t",module_name,"\t Responding Read Request with CurrAddr: %h Data: %8h BurstCounter: %d BurstValue: %d NextAddress: %h",rg_read_packet.araddr,new_data,rg_readburst_counter,rg_read_packet.arlen,address);  `endif
 143            endrule
 144
 145            interface axi_slave= s_xactor.axi_side;
 146         endmodule
 147 endpackage