package MemoryMap;
/*=== Project imports ==== */
import defined_types::*;
- import SoC::*;
- import slow_peripherals::*;
+ import fast_memory_map::*;
+ import slow_memory_map::*;
+ `include "slow_instance_defines.bsv"
+ `include "fast_instance_defines.bsv"
`include "instance_defines.bsv"
`include "core_parameters.bsv"
/*========================= */
-function Tuple2 #(Bool, Bit#(TLog#(Num_Slaves)))
+function Tuple2 #(Bool, Bit#(TLog#(Num_Fast_Slaves)))
fn_addr_to_slave_num (Bit#(`PADDR) addr);
- let ft = FastTuple2;
+ let ft = fn_addr_to_fastslave_num(addr);
Bool isfast = tpl_1(ft);
- Bit#(TLog#(Num_Slaves)) x = tpl_2(ft);
+ Bit#(TLog#(Num_Fast_Slaves)) x = tpl_2(ft);
- let st = SlowTuple2;
+ let st = fn_slow_address_mapping(addr);
Bool isslow = tpl_1(st);
Bit#(TLog#(Num_Slow_Slaves)) y = tpl_2(st);
if (isfast)
endfunction
function Bool is_IO_Addr(Bit#(`PADDR) addr); // TODO Shuold be PADDR
- if(addr>=`DebugBase && addr<=`DebugEnd)
- return (True);
- else if(addr>=`SDRAMMemBase && addr<=`SDRAMMemEnd)
- `ifdef FlexBus
- return (True);
- `else
- return (False);
- `endif
- `ifdef BOOTROM
- else if(addr>=`BootRomBase && addr<=`BootRomEnd)
- return (False);
- `endif
- `ifdef TCMemory
- else if(addr>=`TCMBase && addr<=`TCMEnd)
- return (False);
- `endif
- else
- return True;
+ if(addr>=`DebugBase && addr<=`DebugEnd)
+ return (True);
+ `ifdef SDR0MemBase
+ else if(addr>=`SDR0MemBase && addr<=`SDR0MemEnd)
+ `ifdef FlexBus
+ return (True);
+ `else
+ return (False);
+ `endif
+ `endif
+ `ifdef BOOTROM
+ else if(addr>=`BootRomBase && addr<=`BootRomEnd)
+ return (False);
+ `endif
+ `ifdef TCMemory
+ else if(addr>=`TCMBase && addr<=`TCMEnd)
+ return (False);
+ `endif
+ else
+ return True;
endfunction
endpackage