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take out SDRAM memory-mapping addresses
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Wed, 1 Aug 2018 10:12:52 +0000
(11:12 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Wed, 1 Aug 2018 10:12:52 +0000
(11:12 +0100)
src/core/core_parameters.bsv
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diff --git
a/src/core/core_parameters.bsv
b/src/core/core_parameters.bsv
index d4afdb049c46f3b53f7d0a140973f9d91b28c413..00d476ba42930d2a4d42e4c94299a42727486134 100644
(file)
--- a/
src/core/core_parameters.bsv
+++ b/
src/core/core_parameters.bsv
@@
-405,8
+405,8
@@
`define BootRomEnd 'h00010FFF
`define DMABase 'h00011600
`define DMAEnd 'h000116FF // TODO
`define BootRomEnd 'h00010FFF
`define DMABase 'h00011600
`define DMAEnd 'h000116FF // TODO
-
`define SDRAMCfgBase
'h00011700
- `define SDRAMCfgEnd 'h000117FF // 12 32-bit registers
+
//`define SDRAMCfgBase
'h00011700
+
//
`define SDRAMCfgEnd 'h000117FF // 12 32-bit registers
`define TCMBase 'h00020000 //
`define TCMEnd 'h00040000 // 128KB
`define VMEBase 'h40000000
`define TCMBase 'h00020000 //
`define TCMEnd 'h00040000 // 128KB
`define VMEBase 'h40000000
@@
-418,13
+418,13
@@
`define FlexBusBase 'h50000000
`define FlexBusEnd 'h5FFFFFFF
`endif
`define FlexBusBase 'h50000000
`define FlexBusEnd 'h5FFFFFFF
`endif
- `ifdef FlexBus_verify
-
`define SDRAMMemBase
'h50000000
- `define SDRAMMemEnd 'h5FFFFFFF // 1GB
- `else
-
`define SDRAMMemBase
'h80000000
- `define SDRAMMemEnd 'h8FFFFFFF // 1GB
- `endif
+
//
`ifdef FlexBus_verify
+
//`define SDRAMMemBase
'h50000000
+
//
`define SDRAMMemEnd 'h5FFFFFFF // 1GB
+
//
`else
+
//`define SDRAMMemBase
'h80000000
+
//
`define SDRAMMemEnd 'h8FFFFFFF // 1GB
+
//
`endif
`define AxiExp1Base 'hC0000000
`define AxiExp1End 'hFFFFFFFF
/*=================================================== */
`define AxiExp1Base 'hC0000000
`define AxiExp1End 'hFFFFFFFF
/*=================================================== */