src/peripherals/flexbus/FlexBus_Types.bsv

   1 // Copyright (c) 2017 Bluespec, Inc.  All Rights Reserved
   2
   3 package FlexBus_Types;
   4
   5 // ================================================================
   6 // See export list below
   7 // ================================================================
   8 // Exports
   9
  10 export
  11
  12 // RTL-level interfaces (signals/buses)
  13 FlexBus_Slave_IFC (..),
  14 FlexBus_Master_IFC (..),
  15
  16
  17 // Higher-level enums and structs for the FlexBus
  18 FlexBus_States (..),
  19
  20 FlexBus_Payload (..),
  21 FlexBus_Attr (..),
  22 FlexBus_din (..),
  23 FlexBus_Signals (..),
  24
  25 // Higher-level FIFO-like interfaces for the 5 AXI4 channels,
  26 FlexBus_Register_IFC (..),
  27 FlexBus_Register_Output_IFC (..),
  28 FlexBus_Register_Input_IFC (..),
  29
  30 AXI4_Slave_to_FlexBus_Master_Xactor_IFC (..),
  31
  32 // Transactors from RTL-level interfacecs to FIFO-like interfaces.
  33 mkAXI4_Slave_to_FlexBus_Master_Xactor;
  34
  35 // ================================================================
  36 // BSV library imports
  37
  38 import Vector      :: *;
  39 import FIFOF       :: *;
  40 import GetPut   :: *;
  41 import SpecialFIFOs:: *;
  42 import Connectable :: *;
  43 import ConfigReg :: *;
  44 `include "instance_defines.bsv"
  45
  46 // ----------------
  47 // BSV additional libs
  48
  49 import Semi_FIFOF :: *;
  50 import AXI4_Types   :: *;
  51
  52 //import Memory_AXI4 :: *;
  53
  54 // ****************************************************************
  55 // ****************************************************************
  56 // Section: RTL-level interfaces
  57 // ****************************************************************
  58 // ****************************************************************
  59
  60 // ================================================================
  61 // These are the signal-level interfaces for an FlexBus master.
  62 // The (*..*) attributes ensure that when bsc compiles this to Verilog,
  63 // we get exactly the signals specified in the FlexBus spec.
  64
  65 (* always_ready *)
  66 interface FlexBus_Master_IFC;
  67    // FlexBus External Signals
  68
  69    // AD inout bus separate for now in BSV
  70    (* always_ready *)
  71    interface Get#(Bit#(32)) m_AD;      // out
  72    (* always_ready *)
  73    interface Put#(Bit#(32)) m_din;     // in
  74    (* always_ready *)
  75    interface Get#(Bit#(32)) m_OE32n;   // out 32-bits, same as OEn
  76
  77    (* always_ready *)
  78    interface Get#(Bit#(1))  m_R_Wn;    // out
  79    (* always_ready *)
  80    interface Get#(Bit#(2))  m_TSIZ;    // out
  81
  82    (* always_ready *)
  83    interface Get#(Bit#(6))  m_FBCSn;   // out
  84    (* always_ready *)
  85    interface Get#(Bit#(4))  m_BWEn; // out
  86    (* always_ready *)
  87    interface Get#(Bit#(1))  m_TBSTn;   // out
  88    (* always_ready *)
  89    interface Get#(Bit#(1))  m_OEn;     // out
  90
  91    (* always_ready *)
  92    interface Get#(Bit#(1))  m_ALE;     // out
  93    (* always_ready *)
  94    interface Put#(Bit#(1))  m_tAn;     // in
  95
  96 endinterface: FlexBus_Master_IFC
  97
  98 interface FlexBus_Register_Input_IFC;
  99         method Action reset (Bit#(32) ad_bus);
 100         method Action m_ad_bus (Bit#(32) ad_bus);
 101         method Action m_data_bus (Bit#(32) data_bus);
 102 endinterface: FlexBus_Register_Input_IFC
 103
 104 interface FlexBus_Register_Output_IFC;
 105         (* always_ready, always_enabled *)   method Bit#(6) m_FBCSn();
 106         (* always_ready, always_enabled *)   method Bit#(6) m_SWS();
 107     (* always_ready, always_enabled *)   method Bit#(1) m_SWS_EN();
 108         (* always_ready, always_enabled *)   method Bit#(2) m_ASET();
 109         (* always_ready, always_enabled *)   method Bit#(2) m_RDAH();
 110         (* always_ready, always_enabled *)   method Bit#(2) m_WRAH();
 111         (* always_ready, always_enabled *)   method Bit#(6) m_WS();
 112         (* always_ready, always_enabled *)   method Bit#(1) m_AA();
 113         (* always_ready, always_enabled *)   method Bit#(2) m_PS();
 114         (* always_ready, always_enabled *)   method Bit#(1) m_BEM();
 115         (* always_ready, always_enabled *)   method Bit#(1) m_BSTR();
 116         (* always_ready, always_enabled *)   method Bit#(1) m_BSTW();
 117 endinterface: FlexBus_Register_Output_IFC
 118
 119 interface FlexBus_Register_IFC;
 120         interface FlexBus_Register_Input_IFC inp_side;
 121         interface FlexBus_Register_Output_IFC op_side;
 122 endinterface: FlexBus_Register_IFC
 123
 124 // ================================================================
 125 // These are the signal-level interfaces for an AXI4-Lite slave.
 126 // The (*..*) attributes ensure that when bsc compiles this to Verilog,
 127 // we get exactly the signals specified in the ARM spec.
 128 interface FlexBus_Slave_IFC ;
 129
 130 /*
 131    (* result="AD"       *) interface Put#(Bit#(32))  m_AD;         // out
 132    interface Get#(Bit#(32) m_din;                                  // in
 133
 134    (* result="R_Wn"     *) interface Put#(Bit#(1))   m_R_Wn;       // out
 135    (* result="TSIZ"     *) interface Put#(Bit #(2)   m_TSIZ;       // out
 136
 137    (* result="FBCSn"    *) interface Put#(Bit#(6))   m_FBCSn;      // out
 138    (* result="BEn_BWEn" *) interface Put#(Bit#(4))   m_BE_BWEn;    // out
 139    (* result="TBSTn"    *) interface Put#(Bit#(1))   m_TBSTn;      // out
 140    (* result="OEn"      *) interface Put#(Bit#(1))   m_OEn;        // out
 141
 142    (* result="ALE"      *) interface Put#(Bit#(1))   m_ALE;        // out
 143    interface Get#(Bit#(1) tAn;                                     // in
 144 */
 145
 146    (* always_ready, always_enabled    *)
 147    method Action m_AD     ( (* port="AD"      *) Bit #(32) i_AD);      // in
 148
 149
 150    (* always_ready, always_enabled    *)
 151    method Action m_ALE    ( (* port="ALE"     *) Bit #(1)  i_ALE);     // in
 152
 153    (* always_ready, always_enabled    *)
 154    method Action m_R_Wn   ( (* port="R_Wn"    *) Bit #(1)  i_R_Wn);    // in
 155    (* always_ready, always_enabled    *)
 156    method Action m_TSIZ   ( (* port="TSIZ"    *) Bit #(2)  i_TSIZ);    // in
 157
 158    (* always_ready, always_enabled    *)
 159    method Action m_FBCSn  ( (* port="FBCSn"   *) Bit #(6)  i_FBCSn);   // in
 160    (* always_ready, always_enabled    *)
 161    method Action m_BE_BWEn( (* port="BE_BWEn" *) Bit #(4)  i_BE_BWEn); // in
 162    (* always_ready, always_enabled    *)
 163    method Action m_TBSTn  ( (* port="TBSTn"   *) Bit #(1)  i_TBSTn);   // in
 164    (* always_ready, always_enabled    *)
 165    method Action m_OEn    ( (* port="OEn"     *) Bit #(1)  i_OEn);     // in
 166
 167    (* always_ready, result="din"   *)
 168    method Bit #(32) m_din;                                             // out
 169    (* always_ready, result="TAn"   *)
 170    method Bit #(1) m_TAn;                                              // out
 171
 172 endinterface: FlexBus_Slave_IFC
 173
 174
 175 // ================================================================
 176 // Connecting signal-level interfaces
 177
 178 `ifdef DISABLED_FOR_NOW // TODO. convert to get/put including slave ifc
 179 instance Connectable #(FlexBus_Master_IFC ,
 180                        FlexBus_Slave_IFC  );
 181
 182    module mkConnection #(FlexBus_Master_IFC  flexbus_m,
 183                          FlexBus_Slave_IFC  flexbus_s)
 184                        (Empty);
 185
 186     (* fire_when_enabled, no_implicit_conditions *)
 187     rule rl_flexbus_AD_signals;
 188         flexbus_s.m_AD      (flexbus_m.m_AD);
 189     endrule
 190
 191
 192       (* fire_when_enabled, no_implicit_conditions *)
 193       rule rl_flexbus_Attr_signals;
 194          flexbus_s.m_ALE     (flexbus_m.m_ALE);
 195          flexbus_s.m_R_Wn    (flexbus_m.m_R_Wn);
 196          flexbus_s.m_TSIZ    (flexbus_m.m_TSIZ);
 197       endrule
 198       (* fire_when_enabled, no_implicit_conditions *)
 199       rule rl_flexbus_signals;
 200          flexbus_s.m_FBCSn   (flexbus_m.m_FBCSn);
 201          flexbus_s.m_BE_BWEn (flexbus_m.m_BE_BWEn);
 202          flexbus_s.m_TBSTn   (flexbus_m.m_TBSTn);
 203          flexbus_s.m_OEn     (flexbus_m.m_OEn);
 204       endrule
 205       (* fire_when_enabled *)
 206       //(* fire_when_enabled, no_implicit_conditions *)
 207       rule rl_flexbus_input_signals;
 208          flexbus_m.m_din (flexbus_s.m_din);
 209          flexbus_m.m_TAn (flexbus_s.m_TAn);
 210       endrule
 211
 212    endmodule
 213 endinstance
 214 `endif
 215
 216 // ****************************************************************
 217 // ****************************************************************
 218 // Section: Higher-level FIFO-like interfaces and transactors
 219 // ****************************************************************
 220 // ****************************************************************
 221
 222 // ================================================================
 223 // Higher-level types for payloads (rather than just bits)
 224
 225 typedef enum { IDLE, FlexBus_S0_DEQ_WR_FIFOS, FlexBus_S0_DEQ_RD_FIFOS, FlexBus_S1_ADDR, FlexBus_S2_WRITE, FlexBus_S3_BURST, FlexBus_S4_HOLD } FlexBus_States deriving (Bits, Eq, FShow);
 226 typedef enum { IDLE, FlexBus_S0_CHK_FIFOS, FlexBus_S0_DEQ_FIFOS, FlexBus_WRITE_DUMMY1, FlexBus_WRITE_DUMMY2 } FlexBus_States_wr deriving (Bits, Eq, FShow);
 227 typedef enum { IDLE, FlexBus_S0_CHK_FIFOS, FlexBus_S0_DEQ_FIFOS} FlexBus_States_rd deriving (Bits, Eq, FShow);
 228
 229 //FlexBus Addr. Data Payload
 230
 231 typedef struct {
 232    Bit #(32)     s_AD;                                     // out
 233    } FlexBus_Payload
 234 deriving (Bits, FShow);
 235
 236 typedef struct {
 237    Bit #(32)    din;                                    // in
 238    } FlexBus_din
 239 deriving (Bits, FShow);
 240
 241 //FlexBus Attributes
 242
 243 typedef struct {
 244    Bit #(1)         s_R_Wn;                                   // out
 245    Bit #(2)         s_TSIZ;                                   // out
 246    } FlexBus_Attr
 247 deriving (Bits, FShow);
 248
 249 typedef struct {
 250    Bit #(6)         s_FBCSn;                                  // out
 251    Bit #(4)         s_BEn_BWEn;                               // out
 252    Bit #(1)         s_TBSTn;                                  // out
 253    Bit #(1)         s_OEn;                                    // out
 254    } FlexBus_Signals #(numeric type wd_addr, numeric type wd_data)
 255 deriving (Bits, FShow);
 256
 257 // FlexBus Control Signals
 258
 259 // Bit              s_ALE;                                    // out
 260 // Bit              s_TAn;                                    // in
 261
 262 /* ----------------------------------------------------------------
 263
 264    module mkFlexBusTop (Empty);
 265         AXI4_Slave_to_FlexBus_Master_Xactor_IFC#(56, 64,10)
 266                                                   flexbus_xactor_ifc <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
 267
 268    endmodule
 269
 270
 271 // ---------------------------------------------------------------- */
 272 // AXI4 Lite Slave to FlexBus Master transactor interface
 273
 274 interface AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(numeric type wd_addr,
 275                                        numeric type wd_data,
 276                                        numeric type wd_user);
 277    method Action reset;
 278
 279    // AXI side
 280    interface AXI4_Slave_IFC #(wd_addr, wd_data, wd_user) axi_side;
 281
 282    // FlexBus side
 283    interface FlexBus_Master_IFC flexbus_side;
 284
 285 endinterface: AXI4_Slave_to_FlexBus_Master_Xactor_IFC
 286
 287 // ----------------------------------------------------------------
 288
 289 // AXI4 Lite Slave to FlexBus Master transactor
 290
 291 module mkAXI4_Slave_to_FlexBus_Master_Xactor
 292                 (AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(wd_addr, wd_data, wd_user))
 293    provisos (Add#(a__, 8, wd_addr),
 294         Add#(b__, 64, wd_data),
 295              //Bits#(Bit#(56), wd_addr),
 296              //Bits#(Bit#(64), wd_data),
 297              //Bits#(Bit#(32), wd_fb_addr),
 298              //Bits#(Bit#(32), wd_fb_data),
 299              //Bits#(Inout#(Bit#(32)), a__),
 300             // Bits#(Inout#(Bit#(32)), wd_Fb_addr),
 301              //Bits#(Inout#(Bit#(32)), 48),
 302              Div#(wd_data, 16, 4));
 303    Bool unguarded = True;
 304    Bool guarded   = False;
 305    //let wD_FB_ADDR = valueOf(wd_fb_addr);
 306    //let wD_FB_DATA = valueOf(wd_fb_data);
 307
 308    FlexBus_Register_IFC register_ifc <- mkFlexBus_Registers;
 309
 310    Reg#(Bit#(32))       r_AD            <- mkReg(0);
 311    Reg#(Bit#(32))       r_din           <- mkReg(0);
 312    Reg#(Bit#(1))        r_R_Wn          <- mkReg(1'b1);
 313    Reg#(Bit#(2))        r_TSIZ          <- mkReg(2'b00);
 314    Reg#(Bit#(6))        r_FBCSn         <- mkReg(6'h3F);
 315    Reg#(Bit#(4))        r_BE_BWEn       <- mkReg(4'hF);
 316    Reg#(Bit#(1))        r_TBSTn         <- mkReg(1'b1);
 317    Reg#(Bit#(1))        r_OEn           <- mkReg(1'b1);
 318    Reg#(Bit#(1))        r_ALE           <- mkReg(1'b0);
 319    Reg#(Bit#(1))            r_ext_TAn   <- mkReg(1'b0);
 320    Reg#(Bit#(1))            r_int_TAn   <- mkReg(1'b1);
 321
 322    Reg#(Bit#(2))        r_ASET          <- mkReg(2'b00);
 323    Reg#(Bit#(2))        r_PS            <- mkReg(2'b00);
 324    Reg#(Bit#(3))        r_rpt_cnt       <- mkReg(3'b000);
 325    Reg#(Bit#(2))        r_burst_cnt     <- mkReg(2'b00);
 326    Reg#(Bit#(2))        r_hld_cnt       <- mkReg(2'b00);
 327    Reg#(Bit#(6))        r_WS_cnt        <- mkReg(6'h00);
 328    Reg#(Bit#(6))        r_SWS_cnt       <- mkReg(6'h00);
 329    Reg#(Bit#(wd_addr))  r_awaddr    <- mkReg(0);
 330    Reg#(Bit#(2))        r_awsize    <- mkReg(0);
 331    Reg#(Bit#(wd_addr))  r2_awaddr   <- mkReg(0);
 332    Reg#(Bit#(wd_data))  r_wdata     <- mkReg(0);
 333    Reg#(AXI4_Resp)      r_wrbresp       <- mkReg(AXI4_OKAY);
 334    Reg#(AXI4_Resp)      r_rresp     <- mkReg(AXI4_OKAY);
 335    Reg#(Bit#(wd_data))  r_rd_data        <- mkReg(0);
 336    Reg#(Bit#(TDiv#(wd_data,8))) r1_wstrb <- mkReg(0);
 337    Reg#(Bit#(TDiv#(wd_data,8))) r2_wstrb <- mkReg(0);
 338    Reg#(Bit#(wd_addr))  r_araddr         <- mkReg(0);
 339    Reg#(Bit#(wd_addr))  r2_araddr        <- mkReg(0);
 340    Reg#(Bit#(2))        r_arsize         <- mkReg(0);
 341    Reg#(Bit#(4))        r_arid           <- mkReg(0);
 342    Reg#(Bit#(4))        r_awid           <- mkReg(0);
 343    Reg#(Bit#(1))        wr_pending       <- mkReg(0);
 344    Reg#(Bit#(1))        r_chk_fifos_wr   <- mkReg(0);
 345    Reg#(Bit#(1))        r_chk_fifos_rd   <- mkReg(0);
 346    ConfigReg#(Bit#(1))          rd_wrb      <- mkConfigReg(1);
 347    Reg#(Bool)           r_rready        <- mkReg(False);
 348    Reg#(Bool)           r2_rready       <- mkReg(False);
 349
 350    Reg#(Bool)           r1_awvalid      <- mkReg(False);
 351    Reg#(Bool)           r2_awvalid      <- mkReg(False);
 352    Reg#(Bool)           r1_wvalid       <- mkReg(False);
 353    Reg#(Bool)           r2_wvalid       <- mkReg(False);
 354    Reg#(Bool)               r1_arvalid  <- mkReg(False);
 355    Reg#(Bool)           r2_arvalid      <- mkReg(False);
 356
 357    Reg#(Bool)           r1_OEn          <- mkReg(True);
 358
 359    Reg#(Bit#(8))  r_AD_32bit_data_byte1  <- mkReg(0);
 360    Reg#(Bit#(8))  r_AD_32bit_data_byte2  <- mkReg(0);
 361    Reg#(Bit#(8))  r_AD_32bit_data_byte3  <- mkReg(0);
 362    Reg#(Bit#(8))  r_AD_32bit_data_byte4  <- mkReg(0);
 363
 364    Reg#(Bit#(8))  r_AD_32bit_addr_byte1  <- mkReg(0);
 365    Reg#(Bit#(8))  r_AD_32bit_addr_byte2  <- mkReg(0);
 366    Reg#(Bit#(8))  r_AD_32bit_addr_byte3  <- mkReg(0);
 367    Reg#(Bit#(8))  r_AD_32bit_addr_byte4  <- mkReg(0);
 368
 369    Reg#(Bit#(8))  r_rd_data_32bit_byte1  <- mkReg(0);
 370    Reg#(Bit#(8))  r_rd_data_32bit_byte2  <- mkReg(0);
 371    Reg#(Bit#(8))  r_rd_data_32bit_byte3  <- mkReg(0);
 372    Reg#(Bit#(8))  r_rd_data_32bit_byte4  <- mkReg(0);
 373
 374    Reg#(Bit#(32))  r_MBAR  <- mkReg(32'h04000000);
 375
 376    Reg#(FlexBus_States) flexbus_state <- mkReg(IDLE);
 377    Reg#(FlexBus_States_rd) flexbus_state_rd <- mkReg(FlexBus_S0_CHK_FIFOS);
 378    Reg#(FlexBus_States_wr) flexbus_state_wr <- mkReg(FlexBus_S0_CHK_FIFOS);
 379
 380    // These FIFOs are guarded on BSV side, unguarded on AXI side
 381    FIFOF #(AXI4_Wr_Addr #(wd_addr, wd_user)) f_wr_addr <- mkGFIFOF (unguarded, guarded);
 382    FIFOF #(AXI4_Wr_Data #(wd_data))          f_wr_data <- mkGFIFOF (unguarded, unguarded);
 383    FIFOF #(AXI4_Wr_Resp #(wd_user))          f_wr_resp <- mkGFIFOF (guarded, unguarded);
 384
 385    FIFOF #(AXI4_Rd_Addr #(wd_addr, wd_user)) f_rd_addr <- mkGFIFOF (unguarded, guarded);
 386    FIFOF #(AXI4_Rd_Data #(wd_data, wd_user)) f_rd_data <- mkGFIFOF (guarded, unguarded);
 387
 388    Reg#(Maybe#(Bit#(1)))  c_TAn[2] <- mkCReg(2, tagged Invalid);
 389    Reg#(Maybe#(Bit#(32))) c_din[2] <- mkCReg(2, tagged Invalid);
 390
 391    //TriState#(Bit#(32)) tri_AD_out <- mkTriState(r1_OEn,r_AD);
 392
 393    // ----------------------------------------------------------------
 394
 395    rule rl_OEn;
 396         if (r_OEn == 1'b0)
 397                 r1_OEn <= False;
 398         else
 399                 r1_OEn <= True;
 400    endrule
 401
 402    rule rl_state_S0_CHK_FIFO_RD(flexbus_state_rd == FlexBus_S0_CHK_FIFOS);
 403         `ifdef verbose_debug $display("STATE S0 CHK FIFOS RD FIRED"); `endif
 404         if (f_rd_addr.notEmpty) begin
 405                     register_ifc.inp_side.m_ad_bus(f_rd_addr.first.araddr[31:0]);
 406             flexbus_state_rd <= FlexBus_S0_DEQ_FIFOS;
 407             `ifdef verbose_debug_l2 $display("READ ADDR FIFO WAS READ FIRST  r_araddr=%h \n", f_rd_addr.first.araddr); `endif
 408         end
 409    endrule
 410
 411   (* preempts = "rl_check_read_fifo, rl_check_write_fifo" *)
 412    rule rl_check_read_fifo (r_chk_fifos_rd == 1'b1 && f_rd_addr.notEmpty);
 413                 rd_wrb <= 1'b1;
 414                 r_chk_fifos_rd <= 1'b0;
 415                 r_chk_fifos_wr <= 1'b0;
 416    endrule
 417
 418    rule rl_check_write_fifo(r_chk_fifos_wr == 1'b1 && f_wr_addr.notEmpty && f_wr_data.notEmpty);
 419                     if (f_wr_addr.first.awaddr[31:16] != r_MBAR[31:16]) begin
 420                     rd_wrb <= 1'b0;
 421                     r_chk_fifos_rd <= 1'b0;
 422                     r_chk_fifos_wr <= 1'b0;
 423             end
 424    endrule
 425
 426    rule rl_state_S0_CHK_FIFOS_WR(flexbus_state_wr == FlexBus_S0_CHK_FIFOS);
 427         `ifdef verbose_debug $display("STATE S0 CHK FIFOS WR FIRED"); `endif
 428         if (f_wr_addr.notEmpty && f_wr_data.notEmpty) begin
 429                     if (f_wr_addr.first.awaddr[31:16] == r_MBAR[31:16]) begin
 430                             f_wr_addr.deq; f_wr_data.deq;
 431                     end
 432                     else begin
 433                 flexbus_state_wr <= FlexBus_S0_DEQ_FIFOS;
 434                     end
 435                     register_ifc.inp_side.m_ad_bus(f_wr_addr.first.awaddr[31:0]);
 436                     register_ifc.inp_side.m_data_bus(f_wr_data.first.wdata[31:0]);
 437         end
 438    endrule
 439
 440    rule rl_state_S0_DEQ_FIFOS (flexbus_state_rd == FlexBus_S0_DEQ_FIFOS || flexbus_state_wr == FlexBus_S0_DEQ_FIFOS);
 441         `ifdef verbose_debug $display("STATE S0 DEQ FIFOS FIRED"); `endif
 442         if (rd_wrb == 1'b1) begin
 443                 flexbus_state <= FlexBus_S0_DEQ_RD_FIFOS;
 444                 flexbus_state_rd <= IDLE;
 445                 flexbus_state_wr <= IDLE;
 446         end
 447         else if (rd_wrb == 1'b0) begin
 448                 flexbus_state <= FlexBus_S0_DEQ_WR_FIFOS;
 449                 flexbus_state_rd <= IDLE;
 450                 flexbus_state_wr <= IDLE;
 451         end
 452         if (flexbus_state_rd == FlexBus_S0_DEQ_FIFOS && flexbus_state_wr == FlexBus_S0_DEQ_FIFOS) wr_pending <= 1'b1;
 453    endrule
 454
 455    rule rl_state_S0_DEQ_WR_FIFOS (flexbus_state == FlexBus_S0_DEQ_WR_FIFOS);
 456         `ifdef verbose_debug $display("STATE S0 DEQ WR FIFOS FIRED"); `endif
 457         r_ASET <= register_ifc.op_side.m_ASET;
 458         Bit#(3) v_awsize = 3'b000;
 459         if ((f_wr_addr.notEmpty) )  begin
 460                 r1_awvalid <= f_wr_addr.notEmpty;
 461                 f_wr_addr.deq;
 462         r_chk_fifos_wr <= 1'b1;
 463         r_chk_fifos_rd <= 1'b1;
 464                 AXI4_Wr_Addr#(wd_addr, wd_user) wr_addr = f_wr_addr.first;
 465                 r_awaddr <= f_wr_addr.first.awaddr;
 466                 v_awsize = f_wr_addr.first.awsize;
 467             r_awid <= f_wr_addr.first.awid;
 468                 case (v_awsize) matches
 469                         {3'b000}: r_awsize <= 2'b01;
 470                         {3'b001}: r_awsize <= 2'b10;
 471                         {3'b010}: r_awsize <= 2'b00;
 472                 endcase
 473                 `ifdef verbose_debug_l2 $display("ADDR FIFO WAS NOT EMPTY SO I DEQUEUED r_awaddr=%h \n", r_awaddr); `endif
 474         end
 475         if ((f_wr_data.notEmpty) ) begin
 476                 r1_wvalid <= f_wr_data.notEmpty;
 477                 f_wr_data.deq;
 478                 `ifdef verbose_debug_l2 $display("DATA FIFO WAS NOT EMPTY SO I DEQUEUED\n"); `endif
 479                 AXI4_Wr_Data#(wd_data) wr_data = f_wr_data.first;
 480                 r_wdata <= f_wr_data.first.wdata;
 481                 r1_wstrb <= f_wr_data.first.wstrb;
 482                 `ifdef verbose_debug_l2 $display(" dequeued first r_wdata = %h", r_wdata); `endif
 483         end
 484         if (f_wr_addr.notEmpty && f_wr_data.notEmpty) begin
 485                 flexbus_state <= FlexBus_S1_ADDR;
 486         end
 487    endrule
 488
 489    rule rl_S0_DEQ_RD_FIFOS (flexbus_state == FlexBus_S0_DEQ_RD_FIFOS);
 490         `ifdef verbose_debug $display("STATE S0 DEQ RD FIFOS FIRED"); `endif
 491         r_ASET <= register_ifc.op_side.m_ASET;
 492         Bit#(3) v_arsize = 3'b000;
 493         if ((f_rd_addr.notEmpty) ) begin
 494                 r1_arvalid <= f_rd_addr.notEmpty;
 495                 f_rd_addr.deq;
 496         r_chk_fifos_wr <= 1'b1;
 497         r_chk_fifos_rd <= 1'b1;
 498                 AXI4_Rd_Addr#(wd_addr, wd_user) rd_addr = f_rd_addr.first;
 499                 r_araddr <= f_rd_addr.first.araddr;
 500                 v_arsize = f_rd_addr.first.arsize;
 501             r_arid <= f_rd_addr.first.arid;
 502                 case (v_arsize) matches
 503                         {3'b000}: r_arsize <= 2'b01;
 504                         {3'b001}: r_arsize <= 2'b10;
 505                         {3'b010}: r_arsize <= 2'b00;
 506                 endcase
 507                 r_rd_data_32bit_byte1 <= 0;
 508                 r_rd_data_32bit_byte2 <= 0;
 509                 r_rd_data_32bit_byte3 <= 0;
 510                 r_rd_data_32bit_byte4 <= 0;
 511                 `ifdef verbose_debug_l2 $display("ADDR FIFO WAS NOT EMPTY SO I DEQUEUED r_araddr=%h \n", f_rd_addr.first.araddr); `endif
 512         end
 513         if (f_rd_addr.notEmpty) begin
 514                 flexbus_state <= FlexBus_S1_ADDR;
 515         end
 516    endrule
 517
 518    rule rl_enq_wr_resp;
 519    Bool bready = f_wr_resp.notFull;
 520    if (f_wr_resp.notFull)
 521         f_wr_resp.enq (AXI4_Wr_Resp {bresp:r_wrbresp,
 522                                           buser:0,
 523                                           bid:r_awid});
 524    endrule
 525
 526
 527    rule rl_enq_rd_data;
 528         Bool rready = f_rd_data.notFull;
 529         if (f_rd_data.notFull && r2_rready) begin
 530                 f_rd_data.enq (AXI4_Rd_Data {rdata: r_rd_data,
 531                                                   rresp: r_rresp,
 532                                                   rlast: True,
 533                                                   ruser:0,
 534                           rid:r_arid});
 535                 //AXI4_Slave_IFC.m_rready(True);
 536                 `ifdef verbose_debug $display("RD DATA FIFO WAS NOT FULL SO I ENQUEUED r_rd_data=%h r2_rready= %b\n", r_rd_data, r2_rready); `endif
 537         end
 538    endrule
 539
 540    rule rl_state_S1_ADDR (flexbus_state == FlexBus_S1_ADDR); //Address state
 541         `ifdef verbose_debug $display("STATE S1 FIRED");`endif
 542         r_PS   <= register_ifc.op_side.m_PS;
 543         r_WS_cnt <= register_ifc.op_side.m_WS;
 544         r_OEn <= 1'b1;
 545         r_BE_BWEn <= 4'hF;
 546         r_FBCSn <= 6'h3F;
 547         r_ALE <= 1'b1;
 548         `ifdef verbose_debug_l2 $display(" r_ASET was ASSIGNED = %b", r_ASET); `endif
 549                 if (r_rpt_cnt == 3'b000) begin
 550                         if (r1_arvalid) begin
 551                                 r_AD <= r_araddr[31:0];
 552                                 r_R_Wn <= 1'b1;   // Read
 553                                 r_TSIZ <= r_arsize;
 554                         end
 555                         else if (r1_awvalid && r1_wvalid) begin
 556                                 r_AD <= r_awaddr[31:0];
 557                                 r_R_Wn <= 1'b0;   // WriteBar
 558                                 r_TSIZ <= r_awsize;
 559                         end
 560                 end
 561                 else begin
 562                         if (r_R_Wn == 1'b0) r_AD <= r_awaddr[31:0];
 563                         else r_AD <= r_araddr[31:0];
 564                         r_TBSTn <= 1'b1;
 565                         r_TSIZ <= register_ifc.op_side.m_PS;
 566                 end
 567         if (( r_ASET != 2'b00) ) begin
 568                 r_ASET <= r_ASET - 1;
 569         end
 570         else begin
 571                 flexbus_state <= FlexBus_S2_WRITE;
 572                 if (r_rpt_cnt != 3'b000)
 573                         r_rpt_cnt <= r_rpt_cnt -1;
 574         end
 575    endrule
 576
 577    rule rl_assign_AD_bus_reg (flexbus_state == FlexBus_S1_ADDR) ; // Address an Attributes Phase
 578         `ifdef verbose_debug_l2 $display(" ASSIGN AD BUS FIRED"); `endif
 579
 580         r2_awvalid <= r1_awvalid;
 581         r2_wvalid  <= r1_wvalid;
 582         r2_wstrb   <= r1_wstrb;
 583         r2_arvalid <= r1_arvalid;
 584
 585         r2_araddr <= r_araddr;
 586         r2_awaddr <= r_awaddr;
 587
 588         r_AD_32bit_data_byte1   <= pack(r_wdata[7:0]);
 589         r_AD_32bit_data_byte2   <= pack(r_wdata[15:8]);
 590         r_AD_32bit_data_byte3 <= pack(r_wdata[23:16]);
 591         r_AD_32bit_data_byte4 <= pack(r_wdata[31:24]);
 592         r_AD_32bit_addr_byte1  <= pack(r_awaddr[31:24]);
 593         r_AD_32bit_addr_byte2  <= pack(r_awaddr[23:16]);
 594         r_AD_32bit_addr_byte3  <= pack(r_awaddr[15:8]);
 595         r_AD_32bit_addr_byte4  <= pack(r_awaddr[7:0]);
 596         `ifdef verbose_debug_l2 $display("r_wdata after ASSIGN = %h r_PS = %b r_AD_32bit_data_byte1=%h ", r_wdata, r_PS, r_AD_32bit_data_byte1);
 597         $display("r_awaddr after ASSIGN = %h r_PS = %b r_AD_32bit_addr_byte1=%h ", r_awaddr, r_PS, r_AD_32bit_addr_byte1); `endif
 598    endrule
 599
 600    rule rl_assign_rd_data;
 601         r_rd_data[63:0] <= pack({32'h00000000, r_rd_data_32bit_byte4, r_rd_data_32bit_byte3, r_rd_data_32bit_byte2, r_rd_data_32bit_byte1});
 602         r2_rready <= r_rready;
 603         `ifdef verbose_debug_l2 $display("ASSIGN READ DATA FIRED AND r_rd_data = %h r_rready=%b r2_rready=%b", r_rd_data, r_rready, r2_rready);`endif
 604    endrule
 605
 606    rule rl_read_ext_signals;
 607         if (isValid(c_TAn[1])) begin
 608                 r_ext_TAn <= fromMaybe(?,c_TAn[1]);
 609                 c_TAn[1]<= tagged Invalid;
 610         end
 611         if (isValid(c_din[1])) begin
 612                 r_din <= fromMaybe(?,c_din[1]);
 613                 c_din[1]<= tagged Invalid;
 614         end
 615     //r_din <= tri_AD_out._read;
 616    endrule
 617
 618    rule rl_state_S2_WRITE (flexbus_state == FlexBus_S2_WRITE); //Write Phase
 619         `ifdef verbose_debug $display("STATE S2 FIRED"); `endif
 620         r_ALE <= 1'b0;
 621         r_FBCSn <= register_ifc.op_side.m_FBCSn;
 622         r_SWS_cnt <= register_ifc.op_side.m_SWS;
 623         if (r_R_Wn == 1'b1)
 624                 r_hld_cnt <= register_ifc.op_side.m_RDAH;
 625         else
 626                 r_hld_cnt <= register_ifc.op_side.m_WRAH;
 627                    if (r_R_Wn == 1'b1) begin
 628                         r_OEn <= 1'b0;
 629                         if ((register_ifc.op_side.m_BSTR == 1'b1) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
 630                                 r_TBSTn <= 1'b0;
 631                         end
 632                    end
 633                    else begin
 634                         // ASSIGN WRITE DATA DEPENDING ON BURST INHIBITED OR NOT
 635                         if ((r_rpt_cnt == 3'b000) ) begin
 636                                 if (r_PS == 2'b01) begin
 637                                         r_AD <= pack({r_AD_32bit_data_byte1,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 638                                 end
 639                                 else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
 640                                         r_AD <= pack({r_AD_32bit_data_byte1,r_AD_32bit_data_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 641                                 end
 642                                 else begin
 643                                         r_AD <= pack({r_AD_32bit_data_byte1,r_AD_32bit_data_byte2,r_AD_32bit_data_byte3,r_AD_32bit_data_byte4});
 644                                 end
 645                         end
 646                         else if (r_rpt_cnt == 3'b011) begin
 647                                         r_AD <= pack({r_AD_32bit_data_byte2,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 648                         end
 649                         else if (r_rpt_cnt == 3'b010)
 650                                         r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 651                         else if  (r_rpt_cnt == 3'b001) begin
 652                                 if (r_awsize == 2'b00) begin
 653                                         if ((r_PS == 2'b10) || (r_PS == 2'b11))
 654                                                 r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_data_byte4,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 655                                         else if ((r_PS == 2'b01))
 656                                                 r_AD <= pack({r_AD_32bit_data_byte4,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 657                                         end
 658                                 else if (r_awsize == 2'b10) begin
 659                                         if (r_PS == 2'b01) r_AD <= pack({r_AD_32bit_data_byte2,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 660
 661                                 end
 662                         end
 663                         if (register_ifc.op_side.m_BEM == 1'b1)
 664                                 r_BE_BWEn <= r2_wstrb[3:0];
 665                         if ((register_ifc.op_side.m_BSTW == 1'b1) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
 666                                 r_TBSTn <= 1'b0;
 667                         end
 668                    end
 669                 if (r_WS_cnt == 6'h00) begin
 670                     if (r_ext_TAn == 1'b0) begin
 671                         //r_int_TAn <= 1'b0;
 672                         flexbus_state <= FlexBus_S3_BURST;
 673                     end
 674                     if (register_ifc.op_side.m_AA == 1'b1) begin
 675                         r_int_TAn <= 1'b1;
 676                     end
 677                     r_WS_cnt <= register_ifc.op_side.m_WS;
 678                     if (r_R_Wn == 1'b1) begin
 679                         if (r_arsize == 2'b00) begin
 680                                 if ((register_ifc.op_side.m_BSTR == 1'b1) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
 681                                         if (r_PS == 2'b01) r_burst_cnt <= 2'b11;
 682                                         if ((r_PS == 2'b10)||(r_PS == 2'b11)) r_burst_cnt <= 2'b01;
 683                                 end
 684                                 else if ((register_ifc.op_side.m_BSTR == 1'b0) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
 685                                         if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b100;
 686                                         if (((r_PS == 2'b10)||(r_PS == 2'b11)) && (r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b010;
 687                                 end
 688                         end
 689                         else if (r_arsize == 2'b10) begin
 690                                 if ((register_ifc.op_side.m_BSTR == 1'b1) && (r_PS == 2'b01)) begin
 691                                         r_burst_cnt <= 2'b01;
 692                                 end
 693                                 else if ((register_ifc.op_side.m_BSTR == 1'b0) && (r_PS == 2'b01)) begin
 694                                         if ((r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b010;
 695                                 end
 696                         end
 697                    end
 698                    else begin
 699                         if (r_awsize == 2'b00) begin
 700                                 if ((register_ifc.op_side.m_BSTW == 1'b1) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
 701                                         if (r_PS == 2'b01) r_burst_cnt <= 2'b11;
 702                                         if ((r_PS == 2'b10)||(r_PS == 2'b11)) r_burst_cnt <= 2'b01;
 703                                 end
 704                                 else if ((register_ifc.op_side.m_BSTW == 1'b0) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
 705                                         if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b100;
 706                                         if (((r_PS == 2'b10)||(r_PS == 2'b11)) && (r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b010;
 707                                 end
 708                         end
 709                         else if (r_awsize == 2'b10) begin
 710                                 if ((register_ifc.op_side.m_BSTW == 1'b1) && (r_PS == 2'b01)) begin
 711                                         r_burst_cnt <= 2'b01;
 712                                 end
 713                                 else if ((register_ifc.op_side.m_BSTW == 1'b0) && (r_PS == 2'b01)) begin
 714                                         if ((r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b010;
 715                                 end
 716                         end
 717                    end
 718                 end
 719                 else begin
 720                    r_WS_cnt <= r_WS_cnt -1;
 721              end
 722              `ifdef verbose_debug_l2 $display("r_AD after WRITE = %h r_ASET=%b r_R_Wn= %b r_PS = %b r_AD_32bit_data_byte1=%h ", r_AD, r_ASET, r_R_Wn, r_PS, r_AD_32bit_data_byte1); `endif
 723    endrule
 724
 725    rule rl_state_S3_BURST (flexbus_state == FlexBus_S3_BURST); // Data Phase with/without bursting terminated prematurely externally
 726         `ifdef verbose_debug $display("STATE S3 FIRED"); `endif
 727         `ifdef verbose_debug_l2
 728         $display("r_rpt_cnt in BURST = %b", r_rpt_cnt);
 729         $display("r_burst_cnt in BURST = %b, BSTW=%b", r_burst_cnt,register_ifc.op_side.m_BSTW);
 730         $display (" r_AD in BURST = %h", r_AD);
 731         $display("r_AD after WRITE = %h r_R_Wn= %b r_PS = %b r_AD_32bit_data_byte1=%h r_AD_32bit_data_byte2=%h r_AD_32bit_data_byte3=%h", r_AD, r_R_Wn, r_PS, r_AD_32bit_data_byte1,r_AD_32bit_data_byte2,r_AD_32bit_data_byte3);
 732         `endif
 733         if (r_ext_TAn == 1'b1) begin // premature external termination SLVERR response
 734                 flexbus_state <= FlexBus_S4_HOLD;
 735                 if (r_R_Wn == 1'b1) begin
 736                 r_rresp <= AXI4_SLVERR; //SLVERR
 737         end else begin
 738                 r_wrbresp <= AXI4_SLVERR; //SLVERR
 739         end
 740         end
 741         else if (r_rpt_cnt == 3'b001) begin
 742                 if (r_R_Wn == 1'b1) begin
 743                         if (r_arsize == 2'b00) begin
 744                                 if (r_PS == 2'b01) begin
 745                                         r_rd_data_32bit_byte4 <= r_din[7:0];
 746                                 end
 747                                 else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
 748                                         r_rd_data_32bit_byte3 <= r_din[7:0];
 749                                         r_rd_data_32bit_byte4 <= r_din[15:8];
 750                                 end
 751                         end
 752                         else if (r_arsize == 2'b10) begin
 753                                 if (r_PS == 2'b01)
 754                                         r_rd_data_32bit_byte2 <= r_din[7:0];
 755                         end
 756                         r_rready <= True;
 757                         //r_rpt_cnt <= r_rpt_cnt -1;
 758                 end
 759                 //else
 760                 flexbus_state <= FlexBus_S4_HOLD;
 761                 if (register_ifc.op_side.m_AA == 1'b1) begin // check this functionality  later for now
 762                         r_OEn <= 1'b1;
 763                         r_BE_BWEn <= 4'hF;
 764                         r_FBCSn <= 6'h3F;
 765                 end
 766         end
 767         else if (r_rpt_cnt != 3'b000) begin
 768                 flexbus_state <= FlexBus_S1_ADDR;
 769                 r_ASET <= register_ifc.op_side.m_ASET;
 770                 if (register_ifc.op_side.m_AA == 1'b1) begin
 771                         r_OEn <= 1'b1;
 772                         r_BE_BWEn <= 4'hF;
 773                         r_FBCSn <= 6'h3F;
 774                 end
 775                 if (r_R_Wn == 1'b1) begin
 776                         if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b100))
 777                                 r_rd_data_32bit_byte1 <= r_din[7:0];
 778                         else if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b011))
 779                                 r_rd_data_32bit_byte2 <= r_din[7:0];
 780                         else if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b010)) begin
 781                                 if (r_arsize == 2'b00)
 782                                         r_rd_data_32bit_byte3 <= r_din[7:0];
 783                                 else if (r_arsize == 2'b10)
 784                                         r_rd_data_32bit_byte1 <= r_din[7:0];
 785                         end
 786                         else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
 787                                 r_rd_data_32bit_byte1 <= r_din[7:0];
 788                                 r_rd_data_32bit_byte2 <= r_din[15:8];
 789                         end
 790                 end
 791         end
 792         else if (r_burst_cnt == 2'b01) begin
 793                 if (r_ext_TAn == 1'b1) begin
 794                         flexbus_state <= FlexBus_S4_HOLD;
 795                 end
 796                 else begin
 797                         if (r_R_Wn == 1'b0) begin
 798                                 if (r_awsize == 2'b00) begin
 799                                         if (r_PS == 2'b01)
 800                                                 r_AD <= pack({r_AD_32bit_data_byte4,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 801                                         else if ((r_PS == 2'b10) || (r_PS == 2'b11))
 802                                                 r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_data_byte4,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 803                                         //else
 804                                         //      r_AD <= pack({r_AD_32bit_data_byte1,r_AD_32bit_data_byte2,r_AD_32bit_data_byte3,r_AD_32bit_data_byte4});
 805                                 end
 806                                 else if (r_awsize == 2'b10) begin
 807                                         if (r_PS == 2'b01) r_AD <= pack({r_AD_32bit_data_byte2,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 808                                 end
 809                         end
 810                         else begin
 811                                 if (r_arsize == 2'b00) begin
 812                                         if (r_PS == 2'b01)
 813                                                 r_rd_data_32bit_byte3 <= r_din[7:0];
 814                                         else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
 815                                                 r_rd_data_32bit_byte1 <= r_din[7:0];
 816                                                 r_rd_data_32bit_byte2 <= r_din[15:8];
 817                                         end
 818                                 end
 819                                 else if (r_arsize == 2'b10) begin
 820                                         if (r_PS == 2'b01)
 821                                                 r_rd_data_32bit_byte1 <= r_din[7:0];
 822                                 end
 823                         end
 824                         if (register_ifc.op_side.m_SWS_EN == 1'b1) begin
 825                                 if (r_SWS_cnt == 6'h00) begin
 826                                         r_SWS_cnt <= register_ifc.op_side.m_SWS;
 827                                         if (register_ifc.op_side.m_AA == 1'b1) begin
 828                                                 r_int_TAn <= 1'b1;
 829                                                 r_OEn <= 1'b1;
 830                                                 r_BE_BWEn <= 4'hF;
 831                                                 r_FBCSn <= 6'h3F;
 832                                         end
 833                                         r_burst_cnt <= r_burst_cnt -1;
 834                                         //flexbus_state <= FlexBus_S4_HOLD;
 835                                 end
 836                                 else begin
 837                                         r_SWS_cnt <= r_SWS_cnt -1;
 838                                 end
 839                         end
 840                         else begin
 841                                 if (r_WS_cnt == 6'h00) begin
 842                                         r_WS_cnt <= register_ifc.op_side.m_WS;
 843                                         if (register_ifc.op_side.m_AA == 1'b1) begin
 844                                                 r_int_TAn <= 1'b1;
 845                                                 r_OEn <= 1'b1;
 846                                                 r_BE_BWEn <= 4'hF;
 847                                                 r_FBCSn <= 6'h3F;
 848                                         end
 849                                         r_burst_cnt <= r_burst_cnt -1;
 850                                         //flexbus_state <= FlexBus_S4_HOLD;
 851                                 end
 852                                 else
 853                                         r_WS_cnt <= r_WS_cnt - 1;
 854                         end
 855                 end
 856         end
 857         else if (r_burst_cnt != 2'b00) begin
 858                 if (r_R_Wn == 1'b0) begin
 859                         if ((r_PS == 2'b01) && (r_burst_cnt == 2'b11))
 860                                 r_AD <= pack({r_AD_32bit_data_byte2,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 861                         else if ((r_PS == 2'b01) && (r_burst_cnt == 2'b10)) begin
 862                                 r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 863                         end
 864                         //else if ((r_PS == 2'b01) && (r_burst_cnt == 2'b01))
 865                         //      r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 866                         //else if ((r_PS == 2'b10) || (r_PS == 2'b11))
 867                         //      r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_data_byte4,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 868                 end
 869                 else begin
 870                         if ((r_PS == 2'b01) && (r_burst_cnt == 2'b11))
 871                                 r_rd_data_32bit_byte1 <= r_din[7:0];
 872                         else if ((r_PS == 2'b01) && (r_burst_cnt == 2'b10)) begin
 873                                 r_rd_data_32bit_byte2 <= r_din[7:0];
 874                         end
 875                 end
 876                 if (register_ifc.op_side.m_SWS_EN == 1'b1) begin
 877                         if (r_SWS_cnt == 6'h00) begin
 878                                 r_SWS_cnt <= register_ifc.op_side.m_SWS;
 879                                 if (register_ifc.op_side.m_AA == 1'b1)
 880                                         r_int_TAn <= 1'b1;
 881                                 r_burst_cnt <= r_burst_cnt -1;
 882                         end
 883                         else begin
 884                                 r_SWS_cnt <= r_SWS_cnt -1;
 885                         end
 886                 end
 887                 else begin
 888                         if (r_WS_cnt == 6'h00) begin
 889                                 r_WS_cnt <= register_ifc.op_side.m_WS;
 890                                 if (register_ifc.op_side.m_AA == 1'b1)
 891                                         r_int_TAn <= 1'b1;
 892                                 r_burst_cnt <= r_burst_cnt -1;
 893                         end
 894                         else begin
 895                                 r_WS_cnt <= r_WS_cnt - 1;
 896                         end
 897                end
 898         end
 899         else if (r_burst_cnt == 2'b00) begin
 900                 flexbus_state <= FlexBus_S4_HOLD;
 901                 if (r_R_Wn == 1'b1) begin
 902                         if (r_arsize == 2'b00) begin
 903                                 if (r_PS == 2'b01) begin
 904                                         r_rd_data_32bit_byte4 <= r_din[7:0];
 905                                 end
 906                                 else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
 907                                         r_rd_data_32bit_byte3 <= r_din[7:0];
 908                                         r_rd_data_32bit_byte4 <= r_din[15:8];
 909                                 end
 910                                 else begin
 911                                         r_rd_data_32bit_byte1 <= r_din[7:0];
 912                                         r_rd_data_32bit_byte2 <= r_din[15:8];
 913                                         r_rd_data_32bit_byte3 <= r_din[23:16];
 914                                         r_rd_data_32bit_byte4 <= r_din[31:24];
 915                                 end
 916                         end
 917                         else if (r_arsize == 2'b10) begin
 918                                 if (r_PS == 2'b01)
 919                                         r_rd_data_32bit_byte2 <= r_din[7:0];
 920                                 //if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
 921                                 else begin
 922                                         r_rd_data_32bit_byte1 <= r_din[7:0];
 923                                         r_rd_data_32bit_byte2 <= r_din[15:8];
 924                                 end
 925                         end
 926                         else if (r_arsize == 2'b01) begin
 927                                 r_rd_data_32bit_byte1 <= r_din[7:0];
 928                         end
 929                         r_rready <= True;
 930                 end
 931                 if (register_ifc.op_side.m_AA == 1'b1) begin // check this functionality  later for now
 932                         r_OEn <= 1'b1;
 933                         r_BE_BWEn <= 4'hF;
 934                         r_FBCSn <= 6'h3F;
 935                 end
 936         end
 937    endrule
 938
 939    rule rl_state_S4_HOLD (flexbus_state == FlexBus_S4_HOLD); //Address Phase
 940         `ifdef verbose_debug $display("STATE S4 FIRED");`endif
 941         r_int_TAn <= 1'b1;
 942         r_R_Wn <= 1'b1;
 943         r_OEn <= 1'b1;
 944         r_BE_BWEn <= 4'hF;
 945         r_FBCSn <= 6'h3F;
 946         r_TBSTn <= 1'b1;
 947         if (r_hld_cnt ==  2'b00) begin
 948             if (wr_pending == 1'b1) begin
 949                 flexbus_state <= FlexBus_S0_DEQ_WR_FIFOS;
 950                     flexbus_state_wr <= IDLE;
 951                     flexbus_state_rd <= IDLE;
 952                 wr_pending <= 1'b0;
 953             end
 954             else begin
 955                 flexbus_state <= IDLE;
 956                     flexbus_state_wr <= FlexBus_S0_CHK_FIFOS;
 957                     flexbus_state_rd <= FlexBus_S0_CHK_FIFOS;
 958             end
 959                 r1_arvalid  <= False;
 960                 r1_awvalid  <= False;
 961                 r1_wvalid   <= False;
 962
 963                         r_rready        <= False;
 964                 r_wrbresp       <= AXI4_OKAY;
 965                 r_rresp     <= AXI4_OKAY;
 966                 r_ASET          <= 2'b00;
 967                 r_rpt_cnt       <= 3'b000;
 968                 r_burst_cnt     <= 2'b00;
 969                 r_hld_cnt       <= 2'b00;
 970                 r_WS_cnt        <= 6'h00;
 971                 r_SWS_cnt       <= 6'h00;
 972                 r_awaddr        <= 0;
 973                 r_wdata         <= 0;
 974                 //r_rd_data     <= 0;
 975                 r1_wstrb        <= 0;
 976                 //r2_wstrb      <= 0;
 977                 r_araddr        <= 0;
 978         end
 979         else
 980                 r_hld_cnt <= r_hld_cnt -1;
 981    endrule
 982
 983    // ----------------------------------------------------------------
 984    // INTERFACE
 985
 986    method Action reset;
 987       `ifdef verbose_debug_l2 $display (" I RESET \n"); `endif
 988       f_wr_addr.clear;
 989       f_wr_data.clear;
 990       f_wr_resp.clear;
 991       f_rd_addr.clear;
 992       f_rd_data.clear;
 993
 994       c_TAn[0]<= tagged Invalid;
 995       c_din[0]<= tagged Invalid;
 996    endmethod
 997
 998    // AXI side
 999    interface axi_side = interface AXI4_Slave_IFC;
1000
1001                            // Wr Addr channel
1002                            method Action m_awvalid (Bool           awvalid,
1003                                                     Bit #(wd_addr) awaddr,
1004                                                                 Bit#(3) awsize,
1005                                                     Bit #(wd_user) awuser,
1006                                                                 Bit#(8) awlen,
1007                                                                 Bit#(2) awburst,
1008                                 Bit#(4) awid
1009                                                                 );
1010                   if (awvalid && f_wr_addr.notFull) begin
1011                                         f_wr_addr.enq (AXI4_Wr_Addr {awaddr: awaddr,
1012                                                                    awuser: awuser,
1013                                                                          awlen:awlen,
1014                                                                          awsize:awsize,
1015                                                                          awburst:awburst,
1016                                      awid:awid});
1017                     end
1018                            endmethod
1019
1020                            method Bool m_awready;
1021                               return f_wr_addr.notFull;
1022                            endmethod
1023
1024                            // Wr Data channel
1025                            method Action m_wvalid (Bool                      wvalid,
1026                                                    Bit #(wd_data)            wdata,
1027                                                    Bit #(TDiv #(wd_data, 8)) wstrb,
1028                                                          Bool wlast,
1029                                                          Bit#(4) wid);
1030                              if (wvalid && f_wr_data.notFull) begin
1031                                  f_wr_data.enq (AXI4_Wr_Data {wdata: wdata, wstrb: wstrb, wlast:wlast, wid: wid});
1032                             end
1033                            endmethod
1034
1035                            method Bool m_wready;
1036                               return f_wr_data.notFull;
1037                            endmethod
1038
1039                            // Wr Response channel
1040                            method Bool           m_bvalid = f_wr_resp.notEmpty;
1041                            method Bit #(2)       m_bresp  = pack (f_wr_resp.first.bresp);
1042                            method Bit #(wd_user) m_buser  = f_wr_resp.first.buser;
1043                            method Bit #(4)       m_bid  = f_wr_resp.first.bid;
1044                            method Action m_bready (Bool bready);
1045                               if (bready && f_wr_resp.notEmpty)
1046                                  f_wr_resp.deq;
1047                            endmethod
1048
1049                            // Rd Addr channel
1050                            method Action m_arvalid (Bool           arvalid,
1051                                                     Bit #(wd_addr) araddr,
1052                                                                 Bit#(3)                          arsize,
1053                                                     Bit #(wd_user) aruser,
1054                                                                 Bit#(8)                          arlen,
1055                                                                 Bit#(2)                          arburst,
1056                                 Bit#(4) arid);
1057                                 if (arvalid && f_rd_addr.notFull) begin
1058                                  f_rd_addr.enq (AXI4_Rd_Addr {araddr: araddr,
1059                                                                    aruser: aruser,
1060                                                                          arlen : arlen,
1061                                                                          arsize: arsize,
1062                                                                          arburst:arburst,
1063                                      arid:arid});
1064                         end
1065                            endmethod
1066
1067                            method Bool m_arready;
1068                               return f_rd_addr.notFull;
1069                            endmethod
1070
1071                            // Rd Data channel
1072                            method Bool           m_rvalid = f_rd_data.notEmpty;
1073                            method Bit #(2)       m_rresp  = pack (f_rd_data.first.rresp);
1074                            method Bit #(wd_data) m_rdata  = f_rd_data.first.rdata;
1075                            method Bool m_rlast  = f_rd_data.first.rlast;
1076                            method Bit #(wd_user) m_ruser  = f_rd_data.first.ruser;
1077                            method Bit#(4) m_rid=f_rd_data.first.rid;
1078
1079                            method Action m_rready (Bool rready);
1080                               if (rready && f_rd_data.notEmpty)
1081                                  f_rd_data.deq;
1082                            endmethod
1083                         endinterface;
1084
1085 interface flexbus_side = interface FlexBus_Master_IFC;
1086             //interface io_AD_master = tri_AD_out.io;
1087
1088     interface m_tAn = interface Put
1089         method Action put(Bit#(1) in) if(c_TAn[0] matches tagged Invalid);
1090             c_TAn[0] <= tagged Valid in;
1091         endmethod
1092     endinterface;
1093
1094     interface m_din = interface Put
1095         method Action put(Bit#(32) in) if(c_din[0] matches tagged Invalid);
1096             c_din[0] <= tagged Valid in;
1097         endmethod
1098     endinterface;
1099
1100     interface m_AD = interface Get
1101         method ActionValue#(Bit#(32)) get;
1102             return r_AD;
1103         endmethod
1104     endinterface;
1105
1106     interface m_R_Wn = interface Get
1107         method ActionValue#(Bit#(1)) get;
1108             return r_R_Wn;
1109         endmethod
1110     endinterface;
1111
1112     interface m_TSIZ = interface Get
1113         method ActionValue#(Bit#(2)) get;
1114             return r_TSIZ;
1115         endmethod
1116     endinterface;
1117
1118     interface m_FBCSn = interface Get
1119         method ActionValue#(Bit#(6)) get;
1120             return r_FBCSn;
1121         endmethod
1122     endinterface;
1123
1124     interface m_BWEn = interface Get
1125         method ActionValue#(Bit#(4)) get;
1126             return r_BE_BWEn;
1127         endmethod
1128     endinterface;
1129
1130     interface m_TBSTn = interface Get
1131         method ActionValue#(Bit#(1)) get;
1132             return r_TBSTn;
1133         endmethod
1134     endinterface;
1135
1136     interface m_OE32n = interface Get
1137         method ActionValue#(Bit#(32)) get;
1138             Bit#(32) ten;
1139             for (int i=0; i<32; i=i+1) begin
1140               ten[i] = r_OEn;
1141             end
1142             return ten;
1143         endmethod
1144     endinterface;
1145
1146     interface m_OEn = interface Get
1147         method ActionValue#(Bit#(1)) get;
1148             return r_OEn;
1149         endmethod
1150     endinterface;
1151
1152     interface m_ALE = interface Get
1153         method ActionValue#(Bit#(1)) get;
1154             return r_ALE;
1155         endmethod
1156     endinterface;
1157
1158     //endinterface;
1159
1160 endinterface;
1161
1162 endmodule: mkAXI4_Slave_to_FlexBus_Master_Xactor
1163
1164 module mkFlexBus_Registers (FlexBus_Register_IFC);
1165
1166 // Vectors of Chip Select AR, MR and Control Registers
1167         Vector#(6, Reg#(Bit#(32)) ) vec_addr_regs <- replicateM (mkReg(0));
1168         Vector#(6, Reg#(Bit#(32)) ) vec_mask_regs <- replicateM (mkReg(0));
1169         Vector#(6, Reg#(Bit#(32)) ) vec_cntr_regs <- replicateM (mkReg(0));
1170
1171 // Control Register Fields
1172
1173         Reg#(Bit#(6)) r_FBCSn   <- mkReg(6'h3F);
1174         Reg#(Bit#(6)) r_SWS     <- mkReg(6'h00);
1175         Reg#(Bit#(1)) r_SWS_EN  <- mkReg(1'b0);
1176         Reg#(Bit#(2)) r_ASET    <- mkReg(2'b00);
1177         Reg#(Bit#(2)) r_RDAH    <- mkReg(2'b00);
1178         Reg#(Bit#(2)) r_WRAH    <- mkReg(2'b00);
1179         Reg#(Bit#(6)) r_WS      <- mkReg(6'h00);
1180         Reg#(Bit#(1)) r_AA      <- mkReg(1'b0);
1181         Reg#(Bit#(2)) r_PS      <- mkReg(2'b00);
1182         Reg#(Bit#(1)) r_BEM     <- mkReg(1'b0);
1183         Reg#(Bit#(1)) r_BSTR    <- mkReg(1'b0);
1184         Reg#(Bit#(1)) r_BSTW    <- mkReg(1'b0);
1185
1186         Reg#(Bit#(32)) r_rom_cntr_reg_0 <- mkReg(0);
1187         Reg#(Bit#(32)) r_ad_bus         <- mkReg(32'hFFFFFFFF);
1188         Reg#(Bit#(32)) r_data_bus       <- mkReg(32'h00000000);
1189         Reg#(Bit#(32)) r_MBAR           <- mkReg(32'h04000000);
1190 //------------------------------------------------------------------------
1191
1192         rule rl_write_config_regs;
1193                 Bit#(32) v_MBAR = r_MBAR + 'h0500;
1194                 for (int i=0; i<6; i=i+1) begin
1195                         if ( v_MBAR == r_ad_bus) begin
1196                                 vec_addr_regs[i][31:16] <= r_data_bus[31:16];
1197                         end
1198                         v_MBAR = v_MBAR + 'h04;
1199                         if ( v_MBAR == r_ad_bus) begin
1200                                 vec_mask_regs[i] <= r_data_bus;
1201                         end
1202                         v_MBAR = v_MBAR + 'h04;
1203                         if ( v_MBAR == r_ad_bus) begin
1204                                 vec_cntr_regs[i] <= r_data_bus;
1205                         end
1206                         v_MBAR = v_MBAR + 'h04;
1207                 end
1208         endrule
1209
1210         rule rl_generate_individual_chip_sels;
1211
1212            Bit#(6) chp_sel_vec = 6'h3F;
1213            Bit#(32) r_cntr_reg_sel = 32'h00000000;
1214            for (int i=0; i<6; i=i+1) begin
1215                 if ((~vec_mask_regs[i] & vec_addr_regs[i]) == (~vec_mask_regs[i] & pack({r_ad_bus[31:16],16'h0000}))) begin
1216                         chp_sel_vec[i] = 1'b0;
1217                 end
1218            end
1219            r_FBCSn <= pack({chp_sel_vec[5],chp_sel_vec[4],chp_sel_vec[3],chp_sel_vec[2],chp_sel_vec[1],chp_sel_vec[0]});
1220
1221                 case (pack({chp_sel_vec[5],chp_sel_vec[4],chp_sel_vec[3],chp_sel_vec[2],chp_sel_vec[1],chp_sel_vec[0]})) matches
1222                     {6'b111110}: r_cntr_reg_sel   = vec_cntr_regs[0];
1223                     {6'b111101}: r_cntr_reg_sel   = vec_cntr_regs[1];
1224                     {6'b111011}: r_cntr_reg_sel   = vec_cntr_regs[2];
1225                     {6'b110111}: r_cntr_reg_sel   = vec_cntr_regs[3];
1226                     {6'b101111}: r_cntr_reg_sel   = vec_cntr_regs[4];
1227                     {6'b011111}: r_cntr_reg_sel   = vec_cntr_regs[5];
1228                 endcase
1229
1230                 r_SWS           <= r_cntr_reg_sel[31:26];
1231                 r_SWS_EN        <= r_cntr_reg_sel[23];
1232                 r_ASET          <= r_cntr_reg_sel[21:20];
1233                 r_RDAH          <= r_cntr_reg_sel[19:18];
1234                 r_WRAH          <= r_cntr_reg_sel[17:16];
1235                 //r_WS                  <= r_cntr_reg_sel[15:10];
1236         r_WS        <= 6'h06;
1237                 r_AA            <= r_cntr_reg_sel[8];
1238                 r_PS            <= r_cntr_reg_sel[7:6];
1239                 r_BEM           <= r_cntr_reg_sel[5];
1240                 r_BSTR          <= r_cntr_reg_sel[4];
1241                 r_BSTW          <= r_cntr_reg_sel[3];
1242         endrule
1243 //-------------------------------------------------------------------------
1244 // FlexBus Register Input Interface
1245 interface inp_side = interface FlexBus_Register_Input_IFC;
1246         method Action reset (Bit #(32) ad_bus);
1247                 for (int i=0; i<6; i=i+1)
1248                     vec_addr_regs[i] <= 32'h00000000;
1249                 for (int i=0; i<6; i=i+1)
1250                     vec_mask_regs[i] <= 32'h00000000;
1251                 for (int i=0; i<6; i=i+1)
1252                     vec_cntr_regs[i] <= 32'h00000000;
1253                 r_rom_cntr_reg_0[8] <= ad_bus[2];
1254                 r_rom_cntr_reg_0[7:6] <= ad_bus[1:0];
1255                 r_rom_cntr_reg_0[5] <= ad_bus[3];
1256                 r_rom_cntr_reg_0[15:10] <= 6'h3F;
1257                 r_rom_cntr_reg_0[21:16] <= 6'h3F;
1258                 vec_cntr_regs[0] <= r_rom_cntr_reg_0;
1259         endmethod
1260         method Action m_ad_bus (Bit #(32) ad_bus);
1261                 r_ad_bus <= ad_bus;
1262         endmethod
1263         method Action m_data_bus (Bit #(32) data_bus);
1264                 r_data_bus <= data_bus;
1265         endmethod
1266         endinterface;
1267
1268 // FlexBus Register Output Interface
1269 interface op_side = interface FlexBus_Register_Output_IFC;
1270         method Bit#(6) m_FBCSn ();
1271                return r_FBCSn;
1272         endmethod
1273         method Bit#(6) m_SWS ();
1274                return r_SWS;
1275         endmethod
1276         method Bit#(1) m_SWS_EN ();
1277                return r_SWS_EN;
1278         endmethod
1279         method Bit#(2) m_ASET ();
1280                return r_ASET;
1281         endmethod
1282         method Bit#(2) m_RDAH ();
1283                return r_RDAH;
1284         endmethod
1285         method Bit#(2) m_WRAH ();
1286                return r_WRAH;
1287         endmethod
1288         method Bit#(6) m_WS ();
1289                return r_WS;
1290         endmethod
1291         method Bit#(1) m_AA ();
1292                return r_AA;
1293         endmethod
1294         method Bit#(2) m_PS ();
1295                return r_PS;
1296         endmethod
1297         method Bit#(1) m_BEM ();
1298                return r_BEM;
1299         endmethod
1300         method Bit#(1) m_BSTR ();
1301                return r_BSTR;
1302         endmethod
1303         method Bit#(1) m_BSTW ();
1304                return r_BSTW;
1305         endmethod
1306         endinterface;
1307
1308 endmodule: mkFlexBus_Registers
1309
1310 `ifdef TESTING
1311 module mkVerfn_Top (Empty);
1312
1313 /*
1314     FlexBus_Slave_to_AXI4_Master_Fabric_IFC#(32,32,4)
1315                     verfn_ifc <- mkFlexBus_Slave_to_AXI4_Master_Fabric;
1316     AXI4_Slave_to_FlexBus_Master_Xactor_IFC#(32, 32, 4)
1317               flexbus_xactor_ifc <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
1318
1319     mkConnection(flexbus_xactor_ifc.flexbus_side,verfn_ifc.flexbus_side);
1320 */
1321
1322    AXI4_Slave_to_FlexBus_Master_Xactor_IFC#(56, 64,10)
1323           flexbus_xactor_ifc <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
1324
1325 endmodule
1326 `endif
1327
1328 endpackage