src/peripherals/flexbus/FlexBus_Types.bsv

   1 // Copyright (c) 2017 Bluespec, Inc.  All Rights Reserved
   2
   3 package FlexBus_Types;
   4
   5 // ================================================================
   6 // See export list below
   7 // ================================================================
   8 // Exports
   9
  10 export
  11
  12 // RTL-level interfaces (signals/buses)
  13 FlexBus_Slave_IFC (..),
  14 FlexBus_Master_IFC (..),
  15
  16
  17 // Higher-level enums and structs for the FlexBus
  18 FlexBus_States (..),
  19
  20 FlexBus_Payload (..),
  21 FlexBus_Attr (..),
  22 FlexBus_din (..),
  23 FlexBus_Signals (..),
  24
  25 // Higher-level FIFO-like interfaces for the 5 AXI4 channels,
  26 FlexBus_Register_IFC (..),
  27 FlexBus_Register_Output_IFC (..),
  28 FlexBus_Register_Input_IFC (..),
  29
  30 AXI4_Slave_to_FlexBus_Master_Xactor_IFC (..),
  31
  32 // Transactors from RTL-level interfacecs to FIFO-like interfaces.
  33 mkAXI4_Slave_to_FlexBus_Master_Xactor;
  34
  35 // ================================================================
  36 // BSV library imports
  37
  38 import Vector      :: *;
  39 import FIFOF       :: *;
  40 import SpecialFIFOs:: *;
  41 import Connectable :: *;
  42 import ConfigReg :: *;
  43 `include "defined_parameters.bsv"
  44
  45 // ----------------
  46 // BSV additional libs
  47
  48 import Semi_FIFOF :: *;
  49 import AXI4_Types   :: *;
  50
  51 import Memory_AXI4 :: *;
  52
  53 // ****************************************************************
  54 // ****************************************************************
  55 // Section: RTL-level interfaces
  56 // ****************************************************************
  57 // ****************************************************************
  58
  59 // ================================================================
  60 // These are the signal-level interfaces for an FlexBus master.
  61 // The (*..*) attributes ensure that when bsc compiles this to Verilog,
  62 // we get exactly the signals specified in the FlexBus spec.
  63
  64 interface FlexBus_Master_IFC;
  65    // FlexBus External Signals
  66
  67    // AD inout bus separate for now in BSV
  68    (* always_ready, result="AD"       *)  method Bit #(32)   m_AD;                                // out
  69
  70    //(* always_ready, always_enabled    *)  method Action m_din ((* port="din" *) Bit #(32) din);   // in
  71    method Action m_din ((* port="din" *) Bit #(32) din);   // in
  72
  73    (* always_ready, result="R_Wn"     *)  method Bit #(1)       m_R_Wn;                                   // out
  74    (* always_ready, result="TSIZ"     *)  method Bit #(2)       m_TSIZ;                                   // out
  75
  76    (* always_ready, result="FBCSn"    *)  method Bit #(6)       m_FBCSn;                                  // out
  77    (* always_ready, result="BEn_BWEn" *)  method Bit #(4)       m_BE_BWEn;                                // out
  78    (* always_ready, result="TBSTn"    *)  method Bit #(1)       m_TBSTn;                                  // out
  79    (* always_ready, result="OEn"      *)  method Bit #(1)       m_OEn;                                    // out
  80
  81    (* always_ready, result="ALE"      *)  method Bit #(1)       m_ALE;                                    // out
  82    //(* always_ready, always_enabled    *)  method Action m_TAn ((* port="TAn" *) Bit #(1) tAn);            // in
  83    method Action m_TAn ((* port="TAn" *) Bit #(1) tAn);            // in
  84
  85 endinterface: FlexBus_Master_IFC
  86
  87 interface FlexBus_Register_Input_IFC;
  88         method Action reset (Bit#(32) ad_bus);
  89         method Action m_ad_bus (Bit#(32) ad_bus);
  90         method Action m_data_bus (Bit#(32) data_bus);
  91 endinterface: FlexBus_Register_Input_IFC
  92
  93 interface FlexBus_Register_Output_IFC;
  94         (* always_ready, always_enabled *)   method Bit#(6) m_FBCSn();
  95         (* always_ready, always_enabled *)   method Bit#(6) m_SWS();
  96         (* always_ready, always_enabled *)   method Bit#(1) m_SWS_EN();
  97         (* always_ready, always_enabled *)   method Bit#(2) m_ASET();
  98         (* always_ready, always_enabled *)   method Bit#(2) m_RDAH();
  99         (* always_ready, always_enabled *)   method Bit#(2) m_WRAH();
 100         (* always_ready, always_enabled *)   method Bit#(6) m_WS();
 101         (* always_ready, always_enabled *)   method Bit#(1) m_AA();
 102         (* always_ready, always_enabled *)   method Bit#(2) m_PS();
 103         (* always_ready, always_enabled *)   method Bit#(1) m_BEM();
 104         (* always_ready, always_enabled *)   method Bit#(1) m_BSTR();
 105         (* always_ready, always_enabled *)   method Bit#(1) m_BSTW();
 106 endinterface: FlexBus_Register_Output_IFC
 107
 108 interface FlexBus_Register_IFC;
 109         interface FlexBus_Register_Input_IFC inp_side;
 110         interface FlexBus_Register_Output_IFC op_side;
 111 endinterface: FlexBus_Register_IFC
 112
 113 // ================================================================
 114 // These are the signal-level interfaces for an AXI4-Lite slave.
 115 // The (*..*) attributes ensure that when bsc compiles this to Verilog,
 116 // we get exactly the signals specified in the ARM spec.
 117
 118 interface FlexBus_Slave_IFC ;
 119
 120    (* always_ready, always_enabled    *) method Action m_AD             ( (* port="AD"       *)  Bit #(32)   i_AD);                         // in
 121
 122
 123    (* always_ready, always_enabled    *) method Action m_ALE            ( (* port="ALE"      *)  Bit #(1)         i_ALE);                           // in
 124
 125    (* always_ready, always_enabled    *) method Action m_R_Wn           ( (* port="R_Wn"     *)  Bit #(1)         i_R_Wn);                          // in
 126    (* always_ready, always_enabled    *) method Action m_TSIZ           ( (* port="TSIZ"     *)  Bit #(2)         i_TSIZ);                          // in
 127
 128    (* always_ready, always_enabled    *) method Action m_FBCSn          ( (* port="FBCSn"    *)  Bit #(6)         i_FBCSn);                         // in
 129    (* always_ready, always_enabled    *) method Action m_BE_BWEn        ( (* port="BE_BWEn"  *)  Bit #(4)         i_BE_BWEn);                       // in
 130    (* always_ready, always_enabled    *) method Action m_TBSTn          ( (* port="TBSTn"    *)  Bit #(1)         i_TBSTn);                         // in
 131    (* always_ready, always_enabled    *) method Action m_OEn            ( (* port="OEn"      *)  Bit #(1)         i_OEn);                           // in
 132
 133    (* always_ready, result="din"   *)  method Bit #(32) m_din;                                                // out
 134    (* always_ready, result="TAn"   *)  method Bit #(1) m_TAn;                                                      // out
 135
 136 endinterface: FlexBus_Slave_IFC
 137
 138
 139 // ================================================================
 140 // Connecting signal-level interfaces
 141
 142 instance Connectable #(FlexBus_Master_IFC ,
 143                        FlexBus_Slave_IFC  );
 144
 145    module mkConnection #(FlexBus_Master_IFC  flexbus_m,
 146                          FlexBus_Slave_IFC  flexbus_s)
 147                        (Empty);
 148
 149     (* fire_when_enabled, no_implicit_conditions *)
 150     rule rl_flexbus_AD_signals;
 151         flexbus_s.m_AD      (flexbus_m.m_AD);
 152     endrule
 153
 154
 155       (* fire_when_enabled, no_implicit_conditions *)
 156       rule rl_flexbus_Attr_signals;
 157          flexbus_s.m_ALE     (flexbus_m.m_ALE);
 158          flexbus_s.m_R_Wn    (flexbus_m.m_R_Wn);
 159          flexbus_s.m_TSIZ    (flexbus_m.m_TSIZ);
 160       endrule
 161       (* fire_when_enabled, no_implicit_conditions *)
 162       rule rl_flexbus_signals;
 163          flexbus_s.m_FBCSn   (flexbus_m.m_FBCSn);
 164          flexbus_s.m_BE_BWEn (flexbus_m.m_BE_BWEn);
 165          flexbus_s.m_TBSTn   (flexbus_m.m_TBSTn);
 166          flexbus_s.m_OEn     (flexbus_m.m_OEn);
 167       endrule
 168       (* fire_when_enabled *)
 169       //(* fire_when_enabled, no_implicit_conditions *)
 170       rule rl_flexbus_input_signals;
 171          flexbus_m.m_din (flexbus_s.m_din);
 172          flexbus_m.m_TAn (flexbus_s.m_TAn);
 173       endrule
 174
 175    endmodule
 176 endinstance
 177
 178 // ****************************************************************
 179 // ****************************************************************
 180 // Section: Higher-level FIFO-like interfaces and transactors
 181 // ****************************************************************
 182 // ****************************************************************
 183
 184 // ================================================================
 185 // Higher-level types for payloads (rather than just bits)
 186
 187 typedef enum { IDLE, FlexBus_S0_DEQ_WR_FIFOS, FlexBus_S0_DEQ_RD_FIFOS, FlexBus_S1_ADDR, FlexBus_S2_WRITE, FlexBus_S3_BURST, FlexBus_S4_HOLD } FlexBus_States deriving (Bits, Eq, FShow);
 188 typedef enum { IDLE, FlexBus_S0_CHK_FIFOS, FlexBus_S0_DEQ_FIFOS, FlexBus_WRITE_DUMMY1, FlexBus_WRITE_DUMMY2 } FlexBus_States_wr deriving (Bits, Eq, FShow);
 189 typedef enum { IDLE, FlexBus_S0_CHK_FIFOS, FlexBus_S0_DEQ_FIFOS} FlexBus_States_rd deriving (Bits, Eq, FShow);
 190
 191 //FlexBus Addr. Data Payload
 192
 193 typedef struct {
 194    Bit #(32)     s_AD;                                     // out
 195    } FlexBus_Payload
 196 deriving (Bits, FShow);
 197
 198 typedef struct {
 199    Bit #(32)    din;                                    // in
 200    } FlexBus_din
 201 deriving (Bits, FShow);
 202
 203 //FlexBus Attributes
 204
 205 typedef struct {
 206    Bit #(1)         s_R_Wn;                                   // out
 207    Bit #(2)         s_TSIZ;                                   // out
 208    } FlexBus_Attr
 209 deriving (Bits, FShow);
 210
 211 typedef struct {
 212    Bit #(6)         s_FBCSn;                                  // out
 213    Bit #(4)         s_BEn_BWEn;                               // out
 214    Bit #(1)         s_TBSTn;                                  // out
 215    Bit #(1)         s_OEn;                                    // out
 216    } FlexBus_Signals #(numeric type wd_addr, numeric type wd_data)
 217 deriving (Bits, FShow);
 218
 219 // FlexBus Control Signals
 220
 221 // Bit              s_ALE;                                    // out
 222 // Bit              s_TAn;                                    // in
 223
 224 /* ----------------------------------------------------------------
 225
 226    module mkFlexBusTop (Empty);
 227         AXI4_Slave_to_FlexBus_Master_Xactor_IFC#(56, 64,10)
 228                                                   flexbus_xactor_ifc <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
 229
 230    endmodule
 231
 232
 233 // ---------------------------------------------------------------- */
 234 // AXI4 Lite Slave to FlexBus Master transactor interface
 235
 236 interface AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(numeric type wd_addr,
 237                                        numeric type wd_data,
 238                                        numeric type wd_user);
 239    method Action reset;
 240
 241    // AXI side
 242    interface AXI4_Slave_IFC #(wd_addr, wd_data, wd_user) axi_side;
 243
 244    // FlexBus side
 245    interface FlexBus_Master_IFC flexbus_side;
 246
 247 endinterface: AXI4_Slave_to_FlexBus_Master_Xactor_IFC
 248
 249 // ----------------------------------------------------------------
 250
 251 // AXI4 Lite Slave to FlexBus Master transactor
 252
 253 module mkAXI4_Slave_to_FlexBus_Master_Xactor
 254                 (AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(wd_addr, wd_data, wd_user))
 255    provisos (Add#(a__, 8, wd_addr),
 256         Add#(b__, 64, wd_data),
 257              //Bits#(Bit#(56), wd_addr),
 258              //Bits#(Bit#(64), wd_data),
 259              //Bits#(Bit#(32), wd_fb_addr),
 260              //Bits#(Bit#(32), wd_fb_data),
 261              //Bits#(Inout#(Bit#(32)), a__),
 262             // Bits#(Inout#(Bit#(32)), wd_Fb_addr),
 263              //Bits#(Inout#(Bit#(32)), 48),
 264              Div#(wd_data, 16, 4));
 265    Bool unguarded = True;
 266    Bool guarded   = False;
 267    //let wD_FB_ADDR = valueOf(wd_fb_addr);
 268    //let wD_FB_DATA = valueOf(wd_fb_data);
 269
 270    FlexBus_Register_IFC register_ifc <- mkFlexBus_Registers;
 271
 272    Reg#(Bit#(32))       r_AD            <- mkReg(0);
 273    Reg#(Bit#(32))       r_din           <- mkReg(0);
 274    Reg#(Bit#(1))        r_R_Wn          <- mkReg(1'b1);
 275    Reg#(Bit#(2))        r_TSIZ          <- mkReg(2'b00);
 276    Reg#(Bit#(6))        r_FBCSn         <- mkReg(6'h3F);
 277    Reg#(Bit#(4))        r_BE_BWEn       <- mkReg(4'hF);
 278    Reg#(Bit#(1))        r_TBSTn         <- mkReg(1'b1);
 279    Reg#(Bit#(1))        r_OEn           <- mkReg(1'b1);
 280    Reg#(Bit#(1))        r_ALE           <- mkReg(1'b0);
 281    Reg#(Bit#(1))            r_ext_TAn   <- mkReg(1'b0);
 282    Reg#(Bit#(1))            r_int_TAn   <- mkReg(1'b1);
 283
 284    Reg#(Bit#(2))        r_ASET          <- mkReg(2'b00);
 285    Reg#(Bit#(2))        r_PS            <- mkReg(2'b00);
 286    Reg#(Bit#(3))        r_rpt_cnt       <- mkReg(3'b000);
 287    Reg#(Bit#(2))        r_burst_cnt     <- mkReg(2'b00);
 288    Reg#(Bit#(2))        r_hld_cnt       <- mkReg(2'b00);
 289    Reg#(Bit#(6))        r_WS_cnt        <- mkReg(6'h00);
 290    Reg#(Bit#(6))        r_SWS_cnt       <- mkReg(6'h00);
 291    Reg#(Bit#(wd_addr))  r_awaddr    <- mkReg(0);
 292    Reg#(Bit#(2))        r_awsize    <- mkReg(0);
 293    Reg#(Bit#(wd_addr))  r2_awaddr   <- mkReg(0);
 294    Reg#(Bit#(wd_data))  r_wdata     <- mkReg(0);
 295    Reg#(AXI4_Resp)      r_wrbresp       <- mkReg(AXI4_OKAY);
 296    Reg#(AXI4_Resp)      r_rresp     <- mkReg(AXI4_OKAY);
 297    Reg#(Bit#(wd_data))  r_rd_data        <- mkReg(0);
 298    Reg#(Bit#(TDiv#(wd_data,8))) r1_wstrb <- mkReg(0);
 299    Reg#(Bit#(TDiv#(wd_data,8))) r2_wstrb <- mkReg(0);
 300    Reg#(Bit#(wd_addr))  r_araddr         <- mkReg(0);
 301    Reg#(Bit#(wd_addr))  r2_araddr        <- mkReg(0);
 302    Reg#(Bit#(2))        r_arsize         <- mkReg(0);
 303    Reg#(Bit#(4))        r_arid           <- mkReg(0);
 304    Reg#(Bit#(4))        r_awid           <- mkReg(0);
 305    Reg#(Bit#(1))        wr_pending       <- mkReg(0);
 306    Reg#(Bit#(1))        r_chk_fifos_wr   <- mkReg(0);
 307    Reg#(Bit#(1))        r_chk_fifos_rd   <- mkReg(0);
 308    ConfigReg#(Bit#(1))          rd_wrb      <- mkConfigReg(1);
 309    Reg#(Bool)           r_rready        <- mkReg(False);
 310    Reg#(Bool)           r2_rready       <- mkReg(False);
 311
 312    Reg#(Bool)           r1_awvalid      <- mkReg(False);
 313    Reg#(Bool)           r2_awvalid      <- mkReg(False);
 314    Reg#(Bool)           r1_wvalid       <- mkReg(False);
 315    Reg#(Bool)           r2_wvalid       <- mkReg(False);
 316    Reg#(Bool)               r1_arvalid  <- mkReg(False);
 317    Reg#(Bool)           r2_arvalid      <- mkReg(False);
 318
 319    Reg#(Bool)           r1_OEn          <- mkReg(True);
 320
 321    Reg#(Bit#(8))  r_AD_32bit_data_byte1  <- mkReg(0);
 322    Reg#(Bit#(8))  r_AD_32bit_data_byte2  <- mkReg(0);
 323    Reg#(Bit#(8))  r_AD_32bit_data_byte3  <- mkReg(0);
 324    Reg#(Bit#(8))  r_AD_32bit_data_byte4  <- mkReg(0);
 325
 326    Reg#(Bit#(8))  r_AD_32bit_addr_byte1  <- mkReg(0);
 327    Reg#(Bit#(8))  r_AD_32bit_addr_byte2  <- mkReg(0);
 328    Reg#(Bit#(8))  r_AD_32bit_addr_byte3  <- mkReg(0);
 329    Reg#(Bit#(8))  r_AD_32bit_addr_byte4  <- mkReg(0);
 330
 331    Reg#(Bit#(8))  r_rd_data_32bit_byte1  <- mkReg(0);
 332    Reg#(Bit#(8))  r_rd_data_32bit_byte2  <- mkReg(0);
 333    Reg#(Bit#(8))  r_rd_data_32bit_byte3  <- mkReg(0);
 334    Reg#(Bit#(8))  r_rd_data_32bit_byte4  <- mkReg(0);
 335
 336    Reg#(Bit#(32))  r_MBAR  <- mkReg(32'h04000000);
 337
 338    Reg#(FlexBus_States) flexbus_state <- mkReg(IDLE);
 339    Reg#(FlexBus_States_rd) flexbus_state_rd <- mkReg(FlexBus_S0_CHK_FIFOS);
 340    Reg#(FlexBus_States_wr) flexbus_state_wr <- mkReg(FlexBus_S0_CHK_FIFOS);
 341
 342    // These FIFOs are guarded on BSV side, unguarded on AXI side
 343    FIFOF #(AXI4_Wr_Addr #(wd_addr, wd_user)) f_wr_addr <- mkGFIFOF (unguarded, guarded);
 344    FIFOF #(AXI4_Wr_Data #(wd_data))          f_wr_data <- mkGFIFOF (unguarded, unguarded);
 345    FIFOF #(AXI4_Wr_Resp #(wd_user))          f_wr_resp <- mkGFIFOF (guarded, unguarded);
 346
 347    FIFOF #(AXI4_Rd_Addr #(wd_addr, wd_user)) f_rd_addr <- mkGFIFOF (unguarded, guarded);
 348    FIFOF #(AXI4_Rd_Data #(wd_data, wd_user)) f_rd_data <- mkGFIFOF (guarded, unguarded);
 349
 350    Reg#(Maybe#(Bit#(1)))  c_TAn[2] <- mkCReg(2, tagged Invalid);
 351    Reg#(Maybe#(Bit#(32))) c_din[2] <- mkCReg(2, tagged Invalid);
 352
 353    //TriState#(Bit#(32)) tri_AD_out <- mkTriState(r1_OEn,r_AD);
 354
 355    // ----------------------------------------------------------------
 356
 357    rule rl_OEn;
 358         if (r_OEn == 1'b0)
 359                 r1_OEn <= False;
 360         else
 361                 r1_OEn <= True;
 362    endrule
 363
 364    rule rl_state_S0_CHK_FIFO_RD(flexbus_state_rd == FlexBus_S0_CHK_FIFOS);
 365         `ifdef verbose_debug $display("STATE S0 CHK FIFOS RD FIRED"); `endif
 366         if (f_rd_addr.notEmpty) begin
 367                     register_ifc.inp_side.m_ad_bus(f_rd_addr.first.araddr[31:0]);
 368             flexbus_state_rd <= FlexBus_S0_DEQ_FIFOS;
 369             `ifdef verbose_debug_l2 $display("READ ADDR FIFO WAS READ FIRST  r_araddr=%h \n", f_rd_addr.first.araddr); `endif
 370         end
 371    endrule
 372
 373   (* preempts = "rl_check_read_fifo, rl_check_write_fifo" *)
 374    rule rl_check_read_fifo (r_chk_fifos_rd == 1'b1 && f_rd_addr.notEmpty);
 375                 rd_wrb <= 1'b1;
 376                 r_chk_fifos_rd <= 1'b0;
 377                 r_chk_fifos_wr <= 1'b0;
 378    endrule
 379
 380    rule rl_check_write_fifo(r_chk_fifos_wr == 1'b1 && f_wr_addr.notEmpty && f_wr_data.notEmpty);
 381                     if (f_wr_addr.first.awaddr[31:16] != r_MBAR[31:16]) begin
 382                     rd_wrb <= 1'b0;
 383                     r_chk_fifos_rd <= 1'b0;
 384                     r_chk_fifos_wr <= 1'b0;
 385             end
 386    endrule
 387
 388    rule rl_state_S0_CHK_FIFOS_WR(flexbus_state_wr == FlexBus_S0_CHK_FIFOS);
 389         `ifdef verbose_debug $display("STATE S0 CHK FIFOS WR FIRED"); `endif
 390         if (f_wr_addr.notEmpty && f_wr_data.notEmpty) begin
 391                     if (f_wr_addr.first.awaddr[31:16] == r_MBAR[31:16]) begin
 392                             f_wr_addr.deq; f_wr_data.deq;
 393                     end
 394                     else begin
 395                 flexbus_state_wr <= FlexBus_S0_DEQ_FIFOS;
 396                     end
 397                     register_ifc.inp_side.m_ad_bus(f_wr_addr.first.awaddr[31:0]);
 398                     register_ifc.inp_side.m_data_bus(f_wr_data.first.wdata[31:0]);
 399         end
 400    endrule
 401
 402    rule rl_state_S0_DEQ_FIFOS (flexbus_state_rd == FlexBus_S0_DEQ_FIFOS || flexbus_state_wr == FlexBus_S0_DEQ_FIFOS);
 403         `ifdef verbose_debug $display("STATE S0 DEQ FIFOS FIRED"); `endif
 404         if (rd_wrb == 1'b1) begin
 405                 flexbus_state <= FlexBus_S0_DEQ_RD_FIFOS;
 406                 flexbus_state_rd <= IDLE;
 407                 flexbus_state_wr <= IDLE;
 408         end
 409         else if (rd_wrb == 1'b0) begin
 410                 flexbus_state <= FlexBus_S0_DEQ_WR_FIFOS;
 411                 flexbus_state_rd <= IDLE;
 412                 flexbus_state_wr <= IDLE;
 413         end
 414         if (flexbus_state_rd == FlexBus_S0_DEQ_FIFOS && flexbus_state_wr == FlexBus_S0_DEQ_FIFOS) wr_pending <= 1'b1;
 415    endrule
 416
 417    rule rl_state_S0_DEQ_WR_FIFOS (flexbus_state == FlexBus_S0_DEQ_WR_FIFOS);
 418         `ifdef verbose_debug $display("STATE S0 DEQ WR FIFOS FIRED"); `endif
 419         r_ASET <= register_ifc.op_side.m_ASET;
 420         Bit#(3) v_awsize = 3'b000;
 421         if ((f_wr_addr.notEmpty) )  begin
 422                 r1_awvalid <= f_wr_addr.notEmpty;
 423                 f_wr_addr.deq;
 424         r_chk_fifos_wr <= 1'b1;
 425         r_chk_fifos_rd <= 1'b1;
 426                 AXI4_Wr_Addr#(wd_addr, wd_user) wr_addr = f_wr_addr.first;
 427                 r_awaddr <= f_wr_addr.first.awaddr;
 428                 v_awsize = f_wr_addr.first.awsize;
 429             r_awid <= f_wr_addr.first.awid;
 430                 case (v_awsize) matches
 431                         {3'b000}: r_awsize <= 2'b01;
 432                         {3'b001}: r_awsize <= 2'b10;
 433                         {3'b010}: r_awsize <= 2'b00;
 434                 endcase
 435                 `ifdef verbose_debug_l2 $display("ADDR FIFO WAS NOT EMPTY SO I DEQUEUED r_awaddr=%h \n", r_awaddr); `endif
 436         end
 437         if ((f_wr_data.notEmpty) ) begin
 438                 r1_wvalid <= f_wr_data.notEmpty;
 439                 f_wr_data.deq;
 440                 `ifdef verbose_debug_l2 $display("DATA FIFO WAS NOT EMPTY SO I DEQUEUED\n"); `endif
 441                 AXI4_Wr_Data#(wd_data) wr_data = f_wr_data.first;
 442                 r_wdata <= f_wr_data.first.wdata;
 443                 r1_wstrb <= f_wr_data.first.wstrb;
 444                 `ifdef verbose_debug_l2 $display(" dequeued first r_wdata = %h", r_wdata); `endif
 445         end
 446         if (f_wr_addr.notEmpty && f_wr_data.notEmpty) begin
 447                 flexbus_state <= FlexBus_S1_ADDR;
 448         end
 449    endrule
 450
 451    rule rl_S0_DEQ_RD_FIFOS (flexbus_state == FlexBus_S0_DEQ_RD_FIFOS);
 452         `ifdef verbose_debug $display("STATE S0 DEQ RD FIFOS FIRED"); `endif
 453         r_ASET <= register_ifc.op_side.m_ASET;
 454         Bit#(3) v_arsize = 3'b000;
 455         if ((f_rd_addr.notEmpty) ) begin
 456                 r1_arvalid <= f_rd_addr.notEmpty;
 457                 f_rd_addr.deq;
 458         r_chk_fifos_wr <= 1'b1;
 459         r_chk_fifos_rd <= 1'b1;
 460                 AXI4_Rd_Addr#(wd_addr, wd_user) rd_addr = f_rd_addr.first;
 461                 r_araddr <= f_rd_addr.first.araddr;
 462                 v_arsize = f_rd_addr.first.arsize;
 463             r_arid <= f_rd_addr.first.arid;
 464                 case (v_arsize) matches
 465                         {3'b000}: r_arsize <= 2'b01;
 466                         {3'b001}: r_arsize <= 2'b10;
 467                         {3'b010}: r_arsize <= 2'b00;
 468                 endcase
 469                 r_rd_data_32bit_byte1 <= 0;
 470                 r_rd_data_32bit_byte2 <= 0;
 471                 r_rd_data_32bit_byte3 <= 0;
 472                 r_rd_data_32bit_byte4 <= 0;
 473                 `ifdef verbose_debug_l2 $display("ADDR FIFO WAS NOT EMPTY SO I DEQUEUED r_araddr=%h \n", f_rd_addr.first.araddr); `endif
 474         end
 475         if (f_rd_addr.notEmpty) begin
 476                 flexbus_state <= FlexBus_S1_ADDR;
 477         end
 478    endrule
 479
 480    rule rl_enq_wr_resp;
 481    Bool bready = f_wr_resp.notFull;
 482    if (f_wr_resp.notFull)
 483         f_wr_resp.enq (AXI4_Wr_Resp {bresp:r_wrbresp,
 484                                           buser:0,
 485                                           bid:r_awid});
 486    endrule
 487
 488
 489    rule rl_enq_rd_data;
 490         Bool rready = f_rd_data.notFull;
 491         if (f_rd_data.notFull && r2_rready) begin
 492                 f_rd_data.enq (AXI4_Rd_Data {rdata: r_rd_data,
 493                                                   rresp: r_rresp,
 494                                                   rlast: True,
 495                                                   ruser:0,
 496                           rid:r_arid});
 497                 //AXI4_Slave_IFC.m_rready(True);
 498                 `ifdef verbose_debug $display("RD DATA FIFO WAS NOT FULL SO I ENQUEUED r_rd_data=%h r2_rready= %b\n", r_rd_data, r2_rready); `endif
 499         end
 500    endrule
 501
 502    rule rl_state_S1_ADDR (flexbus_state == FlexBus_S1_ADDR); //Address state
 503         `ifdef verbose_debug $display("STATE S1 FIRED");`endif
 504         r_PS   <= register_ifc.op_side.m_PS;
 505         r_WS_cnt <= register_ifc.op_side.m_WS;
 506         r_OEn <= 1'b1;
 507         r_BE_BWEn <= 4'hF;
 508         r_FBCSn <= 6'h3F;
 509         r_ALE <= 1'b1;
 510         `ifdef verbose_debug_l2 $display(" r_ASET was ASSIGNED = %b", r_ASET); `endif
 511                 if (r_rpt_cnt == 3'b000) begin
 512                         if (r1_arvalid) begin
 513                                 r_AD <= r_araddr[31:0];
 514                                 r_R_Wn <= 1'b1;   // Read
 515                                 r_TSIZ <= r_arsize;
 516                         end
 517                         else if (r1_awvalid && r1_wvalid) begin
 518                                 r_AD <= r_awaddr[31:0];
 519                                 r_R_Wn <= 1'b0;   // WriteBar
 520                                 r_TSIZ <= r_awsize;
 521                         end
 522                 end
 523                 else begin
 524                         if (r_R_Wn == 1'b0) r_AD <= r_awaddr[31:0];
 525                         else r_AD <= r_araddr[31:0];
 526                         r_TBSTn <= 1'b1;
 527                         r_TSIZ <= register_ifc.op_side.m_PS;
 528                 end
 529         if (( r_ASET != 2'b00) ) begin
 530                 r_ASET <= r_ASET - 1;
 531         end
 532         else begin
 533                 flexbus_state <= FlexBus_S2_WRITE;
 534                 if (r_rpt_cnt != 3'b000)
 535                         r_rpt_cnt <= r_rpt_cnt -1;
 536         end
 537    endrule
 538
 539    rule rl_assign_AD_bus_reg (flexbus_state == FlexBus_S1_ADDR) ; // Address an Attributes Phase
 540         `ifdef verbose_debug_l2 $display(" ASSIGN AD BUS FIRED"); `endif
 541
 542         r2_awvalid <= r1_awvalid;
 543         r2_wvalid  <= r1_wvalid;
 544         r2_wstrb   <= r1_wstrb;
 545         r2_arvalid <= r1_arvalid;
 546
 547         r2_araddr <= r_araddr;
 548         r2_awaddr <= r_awaddr;
 549
 550         r_AD_32bit_data_byte1   <= pack(r_wdata[7:0]);
 551         r_AD_32bit_data_byte2   <= pack(r_wdata[15:8]);
 552         r_AD_32bit_data_byte3 <= pack(r_wdata[23:16]);
 553         r_AD_32bit_data_byte4 <= pack(r_wdata[31:24]);
 554         r_AD_32bit_addr_byte1  <= pack(r_awaddr[31:24]);
 555         r_AD_32bit_addr_byte2  <= pack(r_awaddr[23:16]);
 556         r_AD_32bit_addr_byte3  <= pack(r_awaddr[15:8]);
 557         r_AD_32bit_addr_byte4  <= pack(r_awaddr[7:0]);
 558         `ifdef verbose_debug_l2 $display("r_wdata after ASSIGN = %h r_PS = %b r_AD_32bit_data_byte1=%h ", r_wdata, r_PS, r_AD_32bit_data_byte1);
 559         $display("r_awaddr after ASSIGN = %h r_PS = %b r_AD_32bit_addr_byte1=%h ", r_awaddr, r_PS, r_AD_32bit_addr_byte1); `endif
 560    endrule
 561
 562    rule rl_assign_rd_data;
 563         r_rd_data[63:0] <= pack({32'h00000000, r_rd_data_32bit_byte4, r_rd_data_32bit_byte3, r_rd_data_32bit_byte2, r_rd_data_32bit_byte1});
 564         r2_rready <= r_rready;
 565         `ifdef verbose_debug_l2 $display("ASSIGN READ DATA FIRED AND r_rd_data = %h r_rready=%b r2_rready=%b", r_rd_data, r_rready, r2_rready);`endif
 566    endrule
 567
 568    rule rl_read_ext_signals;
 569         if (isValid(c_TAn[1])) begin
 570                 r_ext_TAn <= fromMaybe(?,c_TAn[1]);
 571                 c_TAn[1]<= tagged Invalid;
 572         end
 573         if (isValid(c_din[1])) begin
 574                 r_din <= fromMaybe(?,c_din[1]);
 575                 c_din[1]<= tagged Invalid;
 576         end
 577     //r_din <= tri_AD_out._read;
 578    endrule
 579
 580    rule rl_state_S2_WRITE (flexbus_state == FlexBus_S2_WRITE); //Write Phase
 581         `ifdef verbose_debug $display("STATE S2 FIRED"); `endif
 582         r_ALE <= 1'b0;
 583         r_FBCSn <= register_ifc.op_side.m_FBCSn;
 584         r_SWS_cnt <= register_ifc.op_side.m_SWS;
 585         if (r_R_Wn == 1'b1)
 586                 r_hld_cnt <= register_ifc.op_side.m_RDAH;
 587         else
 588                 r_hld_cnt <= register_ifc.op_side.m_WRAH;
 589                    if (r_R_Wn == 1'b1) begin
 590                         r_OEn <= 1'b0;
 591                         if ((register_ifc.op_side.m_BSTR == 1'b1) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
 592                                 r_TBSTn <= 1'b0;
 593                         end
 594                    end
 595                    else begin
 596                         // ASSIGN WRITE DATA DEPENDING ON BURST INHIBITED OR NOT
 597                         if ((r_rpt_cnt == 3'b000) ) begin
 598                                 if (r_PS == 2'b01) begin
 599                                         r_AD <= pack({r_AD_32bit_data_byte1,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 600                                 end
 601                                 else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
 602                                         r_AD <= pack({r_AD_32bit_data_byte1,r_AD_32bit_data_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 603                                 end
 604                                 else begin
 605                                         r_AD <= pack({r_AD_32bit_data_byte1,r_AD_32bit_data_byte2,r_AD_32bit_data_byte3,r_AD_32bit_data_byte4});
 606                                 end
 607                         end
 608                         else if (r_rpt_cnt == 3'b011) begin
 609                                         r_AD <= pack({r_AD_32bit_data_byte2,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 610                         end
 611                         else if (r_rpt_cnt == 3'b010)
 612                                         r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 613                         else if  (r_rpt_cnt == 3'b001) begin
 614                                 if (r_awsize == 2'b00) begin
 615                                         if ((r_PS == 2'b10) || (r_PS == 2'b11))
 616                                                 r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_data_byte4,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 617                                         else if ((r_PS == 2'b01))
 618                                                 r_AD <= pack({r_AD_32bit_data_byte4,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 619                                         end
 620                                 else if (r_awsize == 2'b10) begin
 621                                         if (r_PS == 2'b01) r_AD <= pack({r_AD_32bit_data_byte2,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 622
 623                                 end
 624                         end
 625                         if (register_ifc.op_side.m_BEM == 1'b1)
 626                                 r_BE_BWEn <= r2_wstrb[3:0];
 627                         if ((register_ifc.op_side.m_BSTW == 1'b1) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
 628                                 r_TBSTn <= 1'b0;
 629                         end
 630                    end
 631                 if (r_WS_cnt == 6'h00) begin
 632                     if (r_ext_TAn == 1'b0) begin
 633                         //r_int_TAn <= 1'b0;
 634                         flexbus_state <= FlexBus_S3_BURST;
 635                     end
 636                     if (register_ifc.op_side.m_AA == 1'b1) begin
 637                         r_int_TAn <= 1'b1;
 638                     end
 639                     r_WS_cnt <= register_ifc.op_side.m_WS;
 640                     if (r_R_Wn == 1'b1) begin
 641                         if (r_arsize == 2'b00) begin
 642                                 if ((register_ifc.op_side.m_BSTR == 1'b1) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
 643                                         if (r_PS == 2'b01) r_burst_cnt <= 2'b11;
 644                                         if ((r_PS == 2'b10)||(r_PS == 2'b11)) r_burst_cnt <= 2'b01;
 645                                 end
 646                                 else if ((register_ifc.op_side.m_BSTR == 1'b0) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
 647                                         if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b100;
 648                                         if (((r_PS == 2'b10)||(r_PS == 2'b11)) && (r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b010;
 649                                 end
 650                         end
 651                         else if (r_arsize == 2'b10) begin
 652                                 if ((register_ifc.op_side.m_BSTR == 1'b1) && (r_PS == 2'b01)) begin
 653                                         r_burst_cnt <= 2'b01;
 654                                 end
 655                                 else if ((register_ifc.op_side.m_BSTR == 1'b0) && (r_PS == 2'b01)) begin
 656                                         if ((r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b010;
 657                                 end
 658                         end
 659                    end
 660                    else begin
 661                         if (r_awsize == 2'b00) begin
 662                                 if ((register_ifc.op_side.m_BSTW == 1'b1) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
 663                                         if (r_PS == 2'b01) r_burst_cnt <= 2'b11;
 664                                         if ((r_PS == 2'b10)||(r_PS == 2'b11)) r_burst_cnt <= 2'b01;
 665                                 end
 666                                 else if ((register_ifc.op_side.m_BSTW == 1'b0) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
 667                                         if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b100;
 668                                         if (((r_PS == 2'b10)||(r_PS == 2'b11)) && (r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b010;
 669                                 end
 670                         end
 671                         else if (r_awsize == 2'b10) begin
 672                                 if ((register_ifc.op_side.m_BSTW == 1'b1) && (r_PS == 2'b01)) begin
 673                                         r_burst_cnt <= 2'b01;
 674                                 end
 675                                 else if ((register_ifc.op_side.m_BSTW == 1'b0) && (r_PS == 2'b01)) begin
 676                                         if ((r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b010;
 677                                 end
 678                         end
 679                    end
 680                 end
 681                 else begin
 682                    r_WS_cnt <= r_WS_cnt -1;
 683              end
 684              `ifdef verbose_debug_l2 $display("r_AD after WRITE = %h r_ASET=%b r_R_Wn= %b r_PS = %b r_AD_32bit_data_byte1=%h ", r_AD, r_ASET, r_R_Wn, r_PS, r_AD_32bit_data_byte1); `endif
 685    endrule
 686
 687    rule rl_state_S3_BURST (flexbus_state == FlexBus_S3_BURST); // Data Phase with/without bursting terminated prematurely externally
 688         `ifdef verbose_debug $display("STATE S3 FIRED"); `endif
 689         `ifdef verbose_debug_l2
 690         $display("r_rpt_cnt in BURST = %b", r_rpt_cnt);
 691         $display("r_burst_cnt in BURST = %b, BSTW=%b", r_burst_cnt,register_ifc.op_side.m_BSTW);
 692         $display (" r_AD in BURST = %h", r_AD);
 693         $display("r_AD after WRITE = %h r_R_Wn= %b r_PS = %b r_AD_32bit_data_byte1=%h r_AD_32bit_data_byte2=%h r_AD_32bit_data_byte3=%h", r_AD, r_R_Wn, r_PS, r_AD_32bit_data_byte1,r_AD_32bit_data_byte2,r_AD_32bit_data_byte3);
 694         `endif
 695         if (r_ext_TAn == 1'b1) begin // premature external termination SLVERR response
 696                 flexbus_state <= FlexBus_S4_HOLD;
 697                 if (r_R_Wn == 1'b1) begin
 698                 r_rresp <= AXI4_SLVERR; //SLVERR
 699         end else begin
 700                 r_wrbresp <= AXI4_SLVERR; //SLVERR
 701         end
 702         end
 703         else if (r_rpt_cnt == 3'b001) begin
 704                 if (r_R_Wn == 1'b1) begin
 705                         if (r_arsize == 2'b00) begin
 706                                 if (r_PS == 2'b01) begin
 707                                         r_rd_data_32bit_byte4 <= r_din[7:0];
 708                                 end
 709                                 else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
 710                                         r_rd_data_32bit_byte3 <= r_din[7:0];
 711                                         r_rd_data_32bit_byte4 <= r_din[15:8];
 712                                 end
 713                         end
 714                         else if (r_arsize == 2'b10) begin
 715                                 if (r_PS == 2'b01)
 716                                         r_rd_data_32bit_byte2 <= r_din[7:0];
 717                         end
 718                         r_rready <= True;
 719                         //r_rpt_cnt <= r_rpt_cnt -1;
 720                 end
 721                 //else
 722                 flexbus_state <= FlexBus_S4_HOLD;
 723                 if (register_ifc.op_side.m_AA == 1'b1) begin // check this functionality  later for now
 724                         r_OEn <= 1'b1;
 725                         r_BE_BWEn <= 4'hF;
 726                         r_FBCSn <= 6'h3F;
 727                 end
 728         end
 729         else if (r_rpt_cnt != 3'b000) begin
 730                 flexbus_state <= FlexBus_S1_ADDR;
 731                 r_ASET <= register_ifc.op_side.m_ASET;
 732                 if (register_ifc.op_side.m_AA == 1'b1) begin
 733                         r_OEn <= 1'b1;
 734                         r_BE_BWEn <= 4'hF;
 735                         r_FBCSn <= 6'h3F;
 736                 end
 737                 if (r_R_Wn == 1'b1) begin
 738                         if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b100))
 739                                 r_rd_data_32bit_byte1 <= r_din[7:0];
 740                         else if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b011))
 741                                 r_rd_data_32bit_byte2 <= r_din[7:0];
 742                         else if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b010)) begin
 743                                 if (r_arsize == 2'b00)
 744                                         r_rd_data_32bit_byte3 <= r_din[7:0];
 745                                 else if (r_arsize == 2'b10)
 746                                         r_rd_data_32bit_byte1 <= r_din[7:0];
 747                         end
 748                         else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
 749                                 r_rd_data_32bit_byte1 <= r_din[7:0];
 750                                 r_rd_data_32bit_byte2 <= r_din[15:8];
 751                         end
 752                 end
 753         end
 754         else if (r_burst_cnt == 2'b01) begin
 755                 if (r_ext_TAn == 1'b1) begin
 756                         flexbus_state <= FlexBus_S4_HOLD;
 757                 end
 758                 else begin
 759                         if (r_R_Wn == 1'b0) begin
 760                                 if (r_awsize == 2'b00) begin
 761                                         if (r_PS == 2'b01)
 762                                                 r_AD <= pack({r_AD_32bit_data_byte4,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 763                                         else if ((r_PS == 2'b10) || (r_PS == 2'b11))
 764                                                 r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_data_byte4,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 765                                         //else
 766                                         //      r_AD <= pack({r_AD_32bit_data_byte1,r_AD_32bit_data_byte2,r_AD_32bit_data_byte3,r_AD_32bit_data_byte4});
 767                                 end
 768                                 else if (r_awsize == 2'b10) begin
 769                                         if (r_PS == 2'b01) r_AD <= pack({r_AD_32bit_data_byte2,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 770                                 end
 771                         end
 772                         else begin
 773                                 if (r_arsize == 2'b00) begin
 774                                         if (r_PS == 2'b01)
 775                                                 r_rd_data_32bit_byte3 <= r_din[7:0];
 776                                         else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
 777                                                 r_rd_data_32bit_byte1 <= r_din[7:0];
 778                                                 r_rd_data_32bit_byte2 <= r_din[15:8];
 779                                         end
 780                                 end
 781                                 else if (r_arsize == 2'b10) begin
 782                                         if (r_PS == 2'b01)
 783                                                 r_rd_data_32bit_byte1 <= r_din[7:0];
 784                                 end
 785                         end
 786                         if (register_ifc.op_side.m_SWS_EN == 1'b1) begin
 787                                 if (r_SWS_cnt == 6'h00) begin
 788                                         r_SWS_cnt <= register_ifc.op_side.m_SWS;
 789                                         if (register_ifc.op_side.m_AA == 1'b1) begin
 790                                                 r_int_TAn <= 1'b1;
 791                                                 r_OEn <= 1'b1;
 792                                                 r_BE_BWEn <= 4'hF;
 793                                                 r_FBCSn <= 6'h3F;
 794                                         end
 795                                         r_burst_cnt <= r_burst_cnt -1;
 796                                         //flexbus_state <= FlexBus_S4_HOLD;
 797                                 end
 798                                 else begin
 799                                         r_SWS_cnt <= r_SWS_cnt -1;
 800                                 end
 801                         end
 802                         else begin
 803                                 if (r_WS_cnt == 6'h00) begin
 804                                         r_WS_cnt <= register_ifc.op_side.m_WS;
 805                                         if (register_ifc.op_side.m_AA == 1'b1) begin
 806                                                 r_int_TAn <= 1'b1;
 807                                                 r_OEn <= 1'b1;
 808                                                 r_BE_BWEn <= 4'hF;
 809                                                 r_FBCSn <= 6'h3F;
 810                                         end
 811                                         r_burst_cnt <= r_burst_cnt -1;
 812                                         //flexbus_state <= FlexBus_S4_HOLD;
 813                                 end
 814                                 else
 815                                         r_WS_cnt <= r_WS_cnt - 1;
 816                         end
 817                 end
 818         end
 819         else if (r_burst_cnt != 2'b00) begin
 820                 if (r_R_Wn == 1'b0) begin
 821                         if ((r_PS == 2'b01) && (r_burst_cnt == 2'b11))
 822                                 r_AD <= pack({r_AD_32bit_data_byte2,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 823                         else if ((r_PS == 2'b01) && (r_burst_cnt == 2'b10)) begin
 824                                 r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 825                         end
 826                         //else if ((r_PS == 2'b01) && (r_burst_cnt == 2'b01))
 827                         //      r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 828                         //else if ((r_PS == 2'b10) || (r_PS == 2'b11))
 829                         //      r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_data_byte4,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 830                 end
 831                 else begin
 832                         if ((r_PS == 2'b01) && (r_burst_cnt == 2'b11))
 833                                 r_rd_data_32bit_byte1 <= r_din[7:0];
 834                         else if ((r_PS == 2'b01) && (r_burst_cnt == 2'b10)) begin
 835                                 r_rd_data_32bit_byte2 <= r_din[7:0];
 836                         end
 837                 end
 838                 if (register_ifc.op_side.m_SWS_EN == 1'b1) begin
 839                         if (r_SWS_cnt == 6'h00) begin
 840                                 r_SWS_cnt <= register_ifc.op_side.m_SWS;
 841                                 if (register_ifc.op_side.m_AA == 1'b1)
 842                                         r_int_TAn <= 1'b1;
 843                                 r_burst_cnt <= r_burst_cnt -1;
 844                         end
 845                         else begin
 846                                 r_SWS_cnt <= r_SWS_cnt -1;
 847                         end
 848                 end
 849                 else begin
 850                         if (r_WS_cnt == 6'h00) begin
 851                                 r_WS_cnt <= register_ifc.op_side.m_WS;
 852                                 if (register_ifc.op_side.m_AA == 1'b1)
 853                                         r_int_TAn <= 1'b1;
 854                                 r_burst_cnt <= r_burst_cnt -1;
 855                         end
 856                         else begin
 857                                 r_WS_cnt <= r_WS_cnt - 1;
 858                         end
 859                end
 860         end
 861         else if (r_burst_cnt == 2'b00) begin
 862                 flexbus_state <= FlexBus_S4_HOLD;
 863                 if (r_R_Wn == 1'b1) begin
 864                         if (r_arsize == 2'b00) begin
 865                                 if (r_PS == 2'b01) begin
 866                                         r_rd_data_32bit_byte4 <= r_din[7:0];
 867                                 end
 868                                 else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
 869                                         r_rd_data_32bit_byte3 <= r_din[7:0];
 870                                         r_rd_data_32bit_byte4 <= r_din[15:8];
 871                                 end
 872                                 else begin
 873                                         r_rd_data_32bit_byte1 <= r_din[7:0];
 874                                         r_rd_data_32bit_byte2 <= r_din[15:8];
 875                                         r_rd_data_32bit_byte3 <= r_din[23:16];
 876                                         r_rd_data_32bit_byte4 <= r_din[31:24];
 877                                 end
 878                         end
 879                         else if (r_arsize == 2'b10) begin
 880                                 if (r_PS == 2'b01)
 881                                         r_rd_data_32bit_byte2 <= r_din[7:0];
 882                                 //if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
 883                                 else begin
 884                                         r_rd_data_32bit_byte1 <= r_din[7:0];
 885                                         r_rd_data_32bit_byte2 <= r_din[15:8];
 886                                 end
 887                         end
 888                         else if (r_arsize == 2'b01) begin
 889                                 r_rd_data_32bit_byte1 <= r_din[7:0];
 890                         end
 891                         r_rready <= True;
 892                 end
 893                 if (register_ifc.op_side.m_AA == 1'b1) begin // check this functionality  later for now
 894                         r_OEn <= 1'b1;
 895                         r_BE_BWEn <= 4'hF;
 896                         r_FBCSn <= 6'h3F;
 897                 end
 898         end
 899    endrule
 900
 901    rule rl_state_S4_HOLD (flexbus_state == FlexBus_S4_HOLD); //Address Phase
 902         `ifdef verbose_debug $display("STATE S4 FIRED");`endif
 903         r_int_TAn <= 1'b1;
 904         r_R_Wn <= 1'b1;
 905         r_OEn <= 1'b1;
 906         r_BE_BWEn <= 4'hF;
 907         r_FBCSn <= 6'h3F;
 908         r_TBSTn <= 1'b1;
 909         if (r_hld_cnt ==  2'b00) begin
 910             if (wr_pending == 1'b1) begin
 911                 flexbus_state <= FlexBus_S0_DEQ_WR_FIFOS;
 912                     flexbus_state_wr <= IDLE;
 913                     flexbus_state_rd <= IDLE;
 914                 wr_pending <= 1'b0;
 915             end
 916             else begin
 917                 flexbus_state <= IDLE;
 918                     flexbus_state_wr <= FlexBus_S0_CHK_FIFOS;
 919                     flexbus_state_rd <= FlexBus_S0_CHK_FIFOS;
 920             end
 921                 r1_arvalid  <= False;
 922                 r1_awvalid  <= False;
 923                 r1_wvalid   <= False;
 924
 925                         r_rready        <= False;
 926                 r_wrbresp       <= AXI4_OKAY;
 927                 r_rresp     <= AXI4_OKAY;
 928                 r_ASET          <= 2'b00;
 929                 r_rpt_cnt       <= 3'b000;
 930                 r_burst_cnt     <= 2'b00;
 931                 r_hld_cnt       <= 2'b00;
 932                 r_WS_cnt        <= 6'h00;
 933                 r_SWS_cnt       <= 6'h00;
 934                 r_awaddr        <= 0;
 935                 r_wdata         <= 0;
 936                 //r_rd_data     <= 0;
 937                 r1_wstrb        <= 0;
 938                 //r2_wstrb      <= 0;
 939                 r_araddr        <= 0;
 940         end
 941         else
 942                 r_hld_cnt <= r_hld_cnt -1;
 943    endrule
 944
 945    // ----------------------------------------------------------------
 946    // INTERFACE
 947
 948    method Action reset;
 949       `ifdef verbose_debug_l2 $display (" I RESET \n"); `endif
 950       f_wr_addr.clear;
 951       f_wr_data.clear;
 952       f_wr_resp.clear;
 953       f_rd_addr.clear;
 954       f_rd_data.clear;
 955
 956       c_TAn[0]<= tagged Invalid;
 957       c_din[0]<= tagged Invalid;
 958    endmethod
 959
 960    // AXI side
 961    interface axi_side = interface AXI4_Slave_IFC;
 962
 963                            // Wr Addr channel
 964                            method Action m_awvalid (Bool           awvalid,
 965                                                     Bit #(wd_addr) awaddr,
 966                                                                 Bit#(3) awsize,
 967                                                     Bit #(wd_user) awuser,
 968                                                                 Bit#(8) awlen,
 969                                                                 Bit#(2) awburst,
 970                                 Bit#(4) awid
 971                                                                 );
 972                   if (awvalid && f_wr_addr.notFull) begin
 973                                         f_wr_addr.enq (AXI4_Wr_Addr {awaddr: awaddr,
 974                                                                    awuser: awuser,
 975                                                                          awlen:awlen,
 976                                                                          awsize:awsize,
 977                                                                          awburst:awburst,
 978                                      awid:awid});
 979                     end
 980                            endmethod
 981
 982                            method Bool m_awready;
 983                               return f_wr_addr.notFull;
 984                            endmethod
 985
 986                            // Wr Data channel
 987                            method Action m_wvalid (Bool                      wvalid,
 988                                                    Bit #(wd_data)            wdata,
 989                                                    Bit #(TDiv #(wd_data, 8)) wstrb,
 990                                                          Bool wlast,
 991                                                          Bit#(4) wid);
 992                              if (wvalid && f_wr_data.notFull) begin
 993                                  f_wr_data.enq (AXI4_Wr_Data {wdata: wdata, wstrb: wstrb, wlast:wlast, wid: wid});
 994                             end
 995                            endmethod
 996
 997                            method Bool m_wready;
 998                               return f_wr_data.notFull;
 999                            endmethod
1000
1001                            // Wr Response channel
1002                            method Bool           m_bvalid = f_wr_resp.notEmpty;
1003                            method Bit #(2)       m_bresp  = pack (f_wr_resp.first.bresp);
1004                            method Bit #(wd_user) m_buser  = f_wr_resp.first.buser;
1005                            method Bit #(4)       m_bid  = f_wr_resp.first.bid;
1006                            method Action m_bready (Bool bready);
1007                               if (bready && f_wr_resp.notEmpty)
1008                                  f_wr_resp.deq;
1009                            endmethod
1010
1011                            // Rd Addr channel
1012                            method Action m_arvalid (Bool           arvalid,
1013                                                     Bit #(wd_addr) araddr,
1014                                                                 Bit#(3)                          arsize,
1015                                                     Bit #(wd_user) aruser,
1016                                                                 Bit#(8)                          arlen,
1017                                                                 Bit#(2)                          arburst,
1018                                 Bit#(4) arid);
1019                                 if (arvalid && f_rd_addr.notFull) begin
1020                                  f_rd_addr.enq (AXI4_Rd_Addr {araddr: araddr,
1021                                                                    aruser: aruser,
1022                                                                          arlen : arlen,
1023                                                                          arsize: arsize,
1024                                                                          arburst:arburst,
1025                                      arid:arid});
1026                         end
1027                            endmethod
1028
1029                            method Bool m_arready;
1030                               return f_rd_addr.notFull;
1031                            endmethod
1032
1033                            // Rd Data channel
1034                            method Bool           m_rvalid = f_rd_data.notEmpty;
1035                            method Bit #(2)       m_rresp  = pack (f_rd_data.first.rresp);
1036                            method Bit #(wd_data) m_rdata  = f_rd_data.first.rdata;
1037                            method Bool m_rlast  = f_rd_data.first.rlast;
1038                            method Bit #(wd_user) m_ruser  = f_rd_data.first.ruser;
1039                            method Bit#(4) m_rid=f_rd_data.first.rid;
1040
1041                            method Action m_rready (Bool rready);
1042                               if (rready && f_rd_data.notEmpty)
1043                                  f_rd_data.deq;
1044                            endmethod
1045                         endinterface;
1046
1047 interface flexbus_side = interface FlexBus_Master_IFC;
1048             //interface io_AD_master = tri_AD_out.io;
1049
1050                          method Action m_TAn (Bit #(1) tAn) if(c_TAn[0] matches tagged Invalid);
1051                                 c_TAn[0] <= tagged Valid tAn;
1052                          endmethod
1053                            method Action m_din ( Bit#(32) din )if(c_din[0] matches tagged Invalid);
1054                                 c_din[0] <= tagged Valid din;
1055                endmethod
1056                          method Bit #(32)   m_AD;
1057                                 return r_AD;
1058              endmethod
1059
1060
1061                          method Bit #(1)       m_R_Wn;                                   // out
1062                                 return r_R_Wn;
1063                          endmethod
1064                          method Bit #(2)       m_TSIZ;                                   // out
1065                                 return r_TSIZ;
1066                          endmethod
1067
1068
1069
1070                          method Bit #(6)       m_FBCSn;                                  // out
1071                                 return r_FBCSn;
1072                          endmethod
1073                          method Bit #(4)       m_BE_BWEn;                                // out
1074                                 return r_BE_BWEn;
1075                          endmethod
1076                          method Bit #(1)       m_TBSTn;                                  // out
1077                                 return r_TBSTn;
1078                          endmethod
1079                          method Bit #(1)       m_OEn;                                    // out
1080                                 return r_OEn;
1081                          endmethod
1082
1083                          method Bit #(1)       m_ALE;                                    // out
1084                                 return r_ALE;
1085                          endmethod
1086                 //endinterface;
1087
1088                         endinterface;
1089
1090 endmodule: mkAXI4_Slave_to_FlexBus_Master_Xactor
1091
1092 module mkFlexBus_Registers (FlexBus_Register_IFC);
1093
1094 // Vectors of Chip Select AR, MR and Control Registers
1095         Vector#(6, Reg#(Bit#(32)) ) vec_addr_regs <- replicateM (mkReg(0));
1096         Vector#(6, Reg#(Bit#(32)) ) vec_mask_regs <- replicateM (mkReg(0));
1097         Vector#(6, Reg#(Bit#(32)) ) vec_cntr_regs <- replicateM (mkReg(0));
1098
1099 // Control Register Fields
1100
1101         Reg#(Bit#(6)) r_FBCSn   <- mkReg(6'h3F);
1102         Reg#(Bit#(6)) r_SWS     <- mkReg(6'h00);
1103         Reg#(Bit#(1)) r_SWS_EN  <- mkReg(1'b0);
1104         Reg#(Bit#(2)) r_ASET    <- mkReg(2'b00);
1105         Reg#(Bit#(2)) r_RDAH    <- mkReg(2'b00);
1106         Reg#(Bit#(2)) r_WRAH    <- mkReg(2'b00);
1107         Reg#(Bit#(6)) r_WS      <- mkReg(6'h00);
1108         Reg#(Bit#(1)) r_AA      <- mkReg(1'b0);
1109         Reg#(Bit#(2)) r_PS      <- mkReg(2'b00);
1110         Reg#(Bit#(1)) r_BEM     <- mkReg(1'b0);
1111         Reg#(Bit#(1)) r_BSTR    <- mkReg(1'b0);
1112         Reg#(Bit#(1)) r_BSTW    <- mkReg(1'b0);
1113
1114         Reg#(Bit#(32)) r_rom_cntr_reg_0 <- mkReg(0);
1115         Reg#(Bit#(32)) r_ad_bus         <- mkReg(32'hFFFFFFFF);
1116         Reg#(Bit#(32)) r_data_bus       <- mkReg(32'h00000000);
1117         Reg#(Bit#(32)) r_MBAR           <- mkReg(32'h04000000);
1118 //------------------------------------------------------------------------
1119
1120         rule rl_write_config_regs;
1121                 Bit#(32) v_MBAR = r_MBAR + 'h0500;
1122                 for (int i=0; i<6; i=i+1) begin
1123                         if ( v_MBAR == r_ad_bus) begin
1124                                 vec_addr_regs[i][31:16] <= r_data_bus[31:16];
1125                         end
1126                         v_MBAR = v_MBAR + 'h04;
1127                         if ( v_MBAR == r_ad_bus) begin
1128                                 vec_mask_regs[i] <= r_data_bus;
1129                         end
1130                         v_MBAR = v_MBAR + 'h04;
1131                         if ( v_MBAR == r_ad_bus) begin
1132                                 vec_cntr_regs[i] <= r_data_bus;
1133                         end
1134                         v_MBAR = v_MBAR + 'h04;
1135                 end
1136         endrule
1137
1138         rule rl_generate_individual_chip_sels;
1139
1140            Bit#(6) chp_sel_vec = 6'h3F;
1141            Bit#(32) r_cntr_reg_sel = 32'h00000000;
1142            for (int i=0; i<6; i=i+1) begin
1143                 if ((~vec_mask_regs[i] & vec_addr_regs[i]) == (~vec_mask_regs[i] & pack({r_ad_bus[31:16],16'h0000}))) begin
1144                         chp_sel_vec[i] = 1'b0;
1145                 end
1146            end
1147            r_FBCSn <= pack({chp_sel_vec[5],chp_sel_vec[4],chp_sel_vec[3],chp_sel_vec[2],chp_sel_vec[1],chp_sel_vec[0]});
1148
1149                 case (pack({chp_sel_vec[5],chp_sel_vec[4],chp_sel_vec[3],chp_sel_vec[2],chp_sel_vec[1],chp_sel_vec[0]})) matches
1150                     {6'b111110}: r_cntr_reg_sel   = vec_cntr_regs[0];
1151                     {6'b111101}: r_cntr_reg_sel   = vec_cntr_regs[1];
1152                     {6'b111011}: r_cntr_reg_sel   = vec_cntr_regs[2];
1153                     {6'b110111}: r_cntr_reg_sel   = vec_cntr_regs[3];
1154                     {6'b101111}: r_cntr_reg_sel   = vec_cntr_regs[4];
1155                     {6'b011111}: r_cntr_reg_sel   = vec_cntr_regs[5];
1156                 endcase
1157
1158                 r_SWS           <= r_cntr_reg_sel[31:26];
1159                 r_SWS_EN        <= r_cntr_reg_sel[23];
1160                 r_ASET          <= r_cntr_reg_sel[21:20];
1161                 r_RDAH          <= r_cntr_reg_sel[19:18];
1162                 r_WRAH          <= r_cntr_reg_sel[17:16];
1163                 //r_WS                  <= r_cntr_reg_sel[15:10];
1164         r_WS        <= 6'h06;
1165                 r_AA            <= r_cntr_reg_sel[8];
1166                 r_PS            <= r_cntr_reg_sel[7:6];
1167                 r_BEM           <= r_cntr_reg_sel[5];
1168                 r_BSTR          <= r_cntr_reg_sel[4];
1169                 r_BSTW          <= r_cntr_reg_sel[3];
1170         endrule
1171 //-------------------------------------------------------------------------
1172 // FlexBus Register Input Interface
1173 interface inp_side = interface FlexBus_Register_Input_IFC;
1174         method Action reset (Bit #(32) ad_bus);
1175                 for (int i=0; i<6; i=i+1)
1176                     vec_addr_regs[i] <= 32'h00000000;
1177                 for (int i=0; i<6; i=i+1)
1178                     vec_mask_regs[i] <= 32'h00000000;
1179                 for (int i=0; i<6; i=i+1)
1180                     vec_cntr_regs[i] <= 32'h00000000;
1181                 r_rom_cntr_reg_0[8] <= ad_bus[2];
1182                 r_rom_cntr_reg_0[7:6] <= ad_bus[1:0];
1183                 r_rom_cntr_reg_0[5] <= ad_bus[3];
1184                 r_rom_cntr_reg_0[15:10] <= 6'h3F;
1185                 r_rom_cntr_reg_0[21:16] <= 6'h3F;
1186                 vec_cntr_regs[0] <= r_rom_cntr_reg_0;
1187         endmethod
1188         method Action m_ad_bus (Bit #(32) ad_bus);
1189                 r_ad_bus <= ad_bus;
1190         endmethod
1191         method Action m_data_bus (Bit #(32) data_bus);
1192                 r_data_bus <= data_bus;
1193         endmethod
1194         endinterface;
1195
1196 // FlexBus Register Output Interface
1197 interface op_side = interface FlexBus_Register_Output_IFC;
1198         method Bit#(6) m_FBCSn ();
1199                return r_FBCSn;
1200         endmethod
1201         method Bit#(6) m_SWS ();
1202                return r_SWS;
1203         endmethod
1204         method Bit#(1) m_SWS_EN ();
1205                return r_SWS_EN;
1206         endmethod
1207         method Bit#(2) m_ASET ();
1208                return r_ASET;
1209         endmethod
1210         method Bit#(2) m_RDAH ();
1211                return r_RDAH;
1212         endmethod
1213         method Bit#(2) m_WRAH ();
1214                return r_WRAH;
1215         endmethod
1216         method Bit#(6) m_WS ();
1217                return r_WS;
1218         endmethod
1219         method Bit#(1) m_AA ();
1220                return r_AA;
1221         endmethod
1222         method Bit#(2) m_PS ();
1223                return r_PS;
1224         endmethod
1225         method Bit#(1) m_BEM ();
1226                return r_BEM;
1227         endmethod
1228         method Bit#(1) m_BSTR ();
1229                return r_BSTR;
1230         endmethod
1231         method Bit#(1) m_BSTW ();
1232                return r_BSTW;
1233         endmethod
1234         endinterface;
1235
1236 endmodule: mkFlexBus_Registers
1237
1238
1239 endpackage