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[shakti-peripherals.git] / src / peripherals / jtagdtm / jtagdtm.bsv
1 /*
2 Copyright (c) 2013, IIT Madras
3 All rights reserved.
4
5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
6
7 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
8 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
9 * Neither the name of IIT Madras nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
10
11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
13 */
14 package jtagdtm;
15 /*====== Package imports ======= */
16 import Clocks::*;
17 import ConcatReg::*;
18 import GetPut::*;
19 import FIFO::*;
20 import FIFOF::*;
21 import SpecialFIFOs::*;
22 import DReg::*;
23 /*======= Project imports ===== */
24 `include "jtagdefines.bsv"
25 //import defined_types::*;
26 /*============================== */
27
28 interface Ifc_jtagdtm;
29 /*======== Scan input pins ===== */
30 (*always_enabled,always_ready*)
31 method Action scan_out_1_i(Bit#(1) scan_out_1);
32 (*always_enabled,always_ready*)
33 method Action scan_out_2_i(Bit#(1) scan_out_2);
34 (*always_enabled,always_ready*)
35 method Action scan_out_3_i(Bit#(1) scan_out_3);
36 (*always_enabled,always_ready*)
37 method Action scan_out_4_i(Bit#(1) scan_out_4);
38 (*always_enabled,always_ready*)
39 method Action scan_out_5_i(Bit#(1) scan_out_5);
40 /*======= SCAN Output Pins ====== */
41 (*always_enabled,always_ready*)
42 method Bit#(1) scan_in_1;
43 (*always_enabled,always_ready*)
44 method Bit#(1) scan_in_2;
45 (*always_enabled,always_ready*)
46 method Bit#(1) scan_in_3;
47 (*always_enabled,always_ready*)
48 method Bit#(1) scan_in_4;
49 (*always_enabled,always_ready*)
50 method Bit#(1) scan_in_5;
51 (*always_enabled,always_ready*)
52 method Bit#(1) scan_en;
53 (*always_enabled,always_ready*)
54 method Bit#(1) scan_mode_te;
55 /*======= BOUNDARY SCAN Output Pin ====== */
56 (*always_enabled,always_ready*)
57 method Action bs_chain_i(Bit#(1) bs_chain);
58 /*======= BOUNDARY SCAN input Pins ====== */
59 (*always_enabled,always_ready*)
60 method Bit#(1) shiftBscan2Edge;
61 (*always_enabled,always_ready*)
62 method Bit#(1) selectJtagInput;
63 (*always_enabled,always_ready*)
64 method Bit#(1) selectJtagOutput;
65 (*always_enabled,always_ready*)
66 method Bit#(1) updateBscan;
67 (*always_enabled,always_ready*)
68 method Bit#(1) bscan_in;
69 (*always_enabled,always_ready*)
70 method Bit#(1) scan_shift_en;
71 /*======== JTAG input pins ===== */
72 (*always_enabled,always_ready*)
73 interface Put#(Bit#(1)) tms;
74 (*always_enabled,always_ready*)
75 interface Put#(Bit#(1)) tdi;
76 /*==== inputs from Sub-modules === */
77 method Action debug_tdi_i(Bit#(1) debug_tdi);
78 /*======= JTAG Output Pins ====== */
79 (*always_enabled,always_ready*)
80 interface Get#(Bit#(1)) tdo;
81 method Bit#(1) tdo_oe;
82 (*always_enabled,always_ready*)
83 interface Get#(Bit#(1)) tck;
84
85 /*======== TAP States ============= */
86 method Bit#(1) shift_dr;
87 method Bit#(1) pause_dr;
88 method Bit#(1) update_dr;
89 method Bit#(1) capture_dr;
90 /*=========== Output for BS Chain ==== */
91 method Bit#(1) extest_select;
92 method Bit#(1) sample_preload_select;
93 method Bit#(1) debug_select;
94 method Bit#(1) debug_tdo;
95 /*================================ */
96 method Action response_from_dm(Bit#(34) responsedm);
97 method ActionValue#(Bit#(40)) request_to_dm;
98
99 endinterface
100
101 function Reg#(t) readOnlyReg(t r);
102 return (interface Reg;
103 method t _read = r;
104 method Action _write(t x) = noAction;
105 endinterface);
106 endfunction
107 function Reg#(Bit#(1)) condwriteSideEffect(Reg#(Bit#(1)) r, Action a);
108 return (interface Reg;
109 method Bit#(1) _read = r._read;
110 method Action _write(Bit#(1) x);
111 r._write(x);
112 if(x==1)
113 a;
114 endmethod
115 endinterface);
116 endfunction
117
118
119
120 typedef enum {TestLogicReset = 4'h0, RunTestIdle = 4'h1, SelectDRScan = 4'h2,
121 CaptureDR = 4'h3, ShiftDR = 4'h4, Exit1DR = 4'h5,
122 PauseDR = 4'h6, Exit2DR = 4'h7, UpdateDR = 4'h8,
123 SelectIRScan = 4'h9, CaptureIR = 4'ha, ShiftIR = 4'hb,
124 Exit1IR = 4'hc, PauseIR = 4'hd, Exit2IR = 4'he,
125 UpdateIR = 4'hf } TapStates deriving(Bits,Eq,FShow);
126
127 (*synthesize*)
128 (*descending_urgency="scan_logic,scan_shift_en"*)
129 module mkjtagdtm(Ifc_jtagdtm);
130 Clock def_clk<-exposeCurrentClock;
131 Clock invert_clock<-invertCurrentClock;
132 Reset invert_reset<-mkAsyncResetFromCR(0,invert_clock);
133
134 /*========= FIFOs to communicate with the DM==== */
135 FIFOF#(Bit#(40)) request_to_DM <-mkUGFIFOF1();
136 FIFOF#(Bit#(34)) response_from_DM <-mkUGFIFOF1();
137 /*================================================ */
138
139 /*=== Wires to capture the input pins === */
140 Wire#(Bit#(1)) wr_tms<-mkDWire(0);
141 Wire#(Bit#(1)) wr_tdi<-mkDWire(0);
142 Reg#(Bit#(1)) wr_debug_tdi<-mkRegA(0);
143 Reg#(Bit#(1)) wr_bs_chain_tdo<-mkRegA(0);
144 /*======================================== */
145
146 Wire#(Bit#(1)) wr_scan_in_1_all <-mkDWire(0);
147 Wire#(Bit#(1)) wr_scan_in_2_out1 <-mkDWire(0);
148 Wire#(Bit#(1)) wr_scan_in_3_out2 <-mkDWire(0);
149 Wire#(Bit#(1)) wr_scan_in_4_out3 <-mkDWire(0);
150 Wire#(Bit#(1)) wr_scan_in_5_out4 <-mkDWire(0);
151 Reg#(Bit#(1)) wr_scan_shift_en[2] <-mkCRegA(2,0);
152
153 Reg#(TapStates) tapstate<-mkRegA(TestLogicReset);
154 Reg#(Bit#(5)) instruction_shiftreg<-mkRegA(0);
155 Reg#(Bit#(5)) instruction<-mkRegA(`IDCODE, clocked_by invert_clock, reset_by invert_reset); // clock this by the inverted clock
156 Reg#(Bit#(1)) bypass_sr<-mkRegA(0);
157 Reg#(Bit#(1)) scan1_sr <-mkRegA(0);
158 Reg#(Bit#(1)) scan2_sr <-mkRegA(0);
159 Reg#(Bit#(1)) scan3_sr <-mkRegA(0);
160 Reg#(Bit#(1)) scan4_sr <-mkRegA(0);
161 Reg#(Bit#(1)) scan5_sr <-mkRegA(0);
162 Reg#(Bit#(1)) scanall_sr<-mkRegA(0);
163 Reg#(Bit#(1)) scan_en_sr<-mkRegA(0);
164 Reg#(Bit#(1)) scan_mode_te_sr<-mkRegA(0);
165 Reg#(Bit#(1)) full_scan_en_sr<-mkRegA(0);
166 Reg#(Bit#(1)) scan_out_1_sr<-mkRegA(0);
167 Reg#(Bit#(1)) scan_out_2_sr<-mkRegA(0);
168 Reg#(Bit#(1)) scan_out_3_sr<-mkRegA(0);
169 Reg#(Bit#(1)) scan_out_4_sr<-mkRegA(0);
170 Reg#(Bit#(1)) scan_out_5_sr<-mkRegA(0);
171 Wire#(Bit#(1)) shiftBscan2Edge_sr<-mkDWire(0);
172 Wire#(Bit#(1)) selectJtagInput_sr<-mkDWire(0);
173 Wire#(Bit#(1)) selectJtagOutput_sr<-mkDWire(0);
174 Wire#(Bit#(1)) updateBscan_sr<-mkDWire(0);
175 Reg#(Bit#(1)) bs_sr<-mkRegA(0);
176 Reg#(Bit#(32)) idcode_sr<-mkRegA(`IDCODEVALUE);
177
178 Wire#(Bool) wr_dmihardreset_generated<-mkDWire(False);
179 Reg#(Bit#(1)) rg_dmihardreset<-mkRegA(0);
180 Reg#(Bit#(1)) dmihardreset=condwriteSideEffect(rg_dmihardreset,wr_dmihardreset_generated._write(True));
181 Wire#(Bool) wr_dmireset_generated<-mkDWire(False);
182 Reg#(Bit#(1)) rg_dmireset<-mkDReg(0);
183 Reg#(Bit#(1)) dmireset=condwriteSideEffect(rg_dmireset,wr_dmireset_generated._write(True));
184 Reg#(Bit#(3)) idle=readOnlyReg(3'd7);
185 Reg#(Bit#(2)) dmistat<-mkRegA(0);
186 Reg#(Bit#(6)) abits =readOnlyReg(6'd6);
187 Reg#(Bit#(4)) version = readOnlyReg('d1);
188 Reg#(Bit#(32)) dtmcontrol=concatReg8(readOnlyReg(14'd0),
189 dmihardreset,dmireset,readOnlyReg(1'd0),
190 idle,readOnlyReg(dmistat),abits,version);
191 Reg#(Bit#(32)) dtmcontrol_shiftreg<-mkRegA({17'd0,3'd7,2'd0,6'd6,4'd1});
192
193 Reg#(Bit#(40)) dmiaccess_shiftreg[2]<-mkCReg(2,'d2);
194 Reg#(Bit#(2)) response_status<-mkReg(0);
195 Reg#(Bool) capture_repsonse_from_dm<-mkRegA(False);
196 Reg#(Bit#(1)) rg_tdo<-mkRegA(0, clocked_by invert_clock, reset_by invert_reset);
197
198 ReadOnly#(TapStates) crossed_tapstate <-mkNullCrossingWire(invert_clock,tapstate);
199 ReadOnly#(Bit#(5)) crossed_instruction_shiftreg<-mkNullCrossingWire(invert_clock,instruction_shiftreg);
200 ReadOnly#(Bit#(5)) crossed_instruction <-mkNullCrossingWire(def_clk,instruction);
201 ReadOnly#(Bit#(1)) crossed_scan_out_1_sr <-mkNullCrossingWire(invert_clock,scan_out_1_sr);
202 ReadOnly#(Bit#(1)) crossed_scan_out_2_sr <-mkNullCrossingWire(invert_clock,scan_out_2_sr);
203 ReadOnly#(Bit#(1)) crossed_scan_out_3_sr <-mkNullCrossingWire(invert_clock,scan_out_3_sr);
204 ReadOnly#(Bit#(1)) crossed_scan_out_4_sr <-mkNullCrossingWire(invert_clock,scan_out_4_sr);
205 ReadOnly#(Bit#(1)) crossed_scan_out_5_sr <-mkNullCrossingWire(invert_clock,scan_out_5_sr);
206 ReadOnly#(Bit#(1)) crossed_scan_en_sr <-mkNullCrossingWire(invert_clock,scan_en_sr);
207 ReadOnly#(Bit#(1)) crossed_scan_mode_te_sr <-mkNullCrossingWire(invert_clock,scan_mode_te_sr);
208 ReadOnly#(Bit#(1)) crossed_full_scan_en_sr <-mkNullCrossingWire(invert_clock,full_scan_en_sr);
209 ReadOnly#(Bit#(1)) crossed_bypass_sr <-mkNullCrossingWire(invert_clock,bypass_sr);
210 ReadOnly#(Bit#(32)) crossed_idcode_sr <-mkNullCrossingWire(invert_clock,idcode_sr);
211 ReadOnly#(Bit#(1)) crossed_bs_chain_tdo <-mkNullCrossingWire(invert_clock,wr_bs_chain_tdo);
212 ReadOnly#(Bit#(1)) crossed_debug_tdi <-mkNullCrossingWire(invert_clock,wr_debug_tdi);
213 ReadOnly#(Bit#(32)) crossed_dtmcontrol_shiftreg<-mkNullCrossingWire(invert_clock,dtmcontrol_shiftreg);
214 ReadOnly#(Bit#(1)) crossed_output_tdo<-mkNullCrossingWire(def_clk,rg_tdo);
215 ReadOnly#(Bit#(40)) crossed_dmiaccess_shiftreg<-mkNullCrossingWire(invert_clock,dmiaccess_shiftreg[0]);
216
217 Bit#(1) bypass_sel = crossed_instruction == `BYPASS?1:0;
218 Bit#(1) scan_en_sel = crossed_instruction == `SCANEN?1:0;
219 Bit#(1) scan_mode_te_sel = crossed_instruction == `SCANMODE_TE?1:0;
220 Bit#(1) scan1_sel = crossed_instruction == `SCAN1?1:0;
221 Bit#(1) scan2_sel = crossed_instruction == `SCAN2?1:0;
222 Bit#(1) scan3_sel = crossed_instruction == `SCAN3?1:0;
223 Bit#(1) scan4_sel = crossed_instruction == `SCAN4?1:0;
224 Bit#(1) scan5_sel = crossed_instruction == `SCAN5?1:0;
225 Bit#(1) scanall_sel = crossed_instruction == `SCANALL?1:0;
226 Bit#(1) full_scan_en_sel = crossed_instruction == `FULLSCANEN?1:0;
227 Bit#(1) idcode_sel = crossed_instruction == `IDCODE?1:0;
228 Bit#(1) dbg_sel = crossed_instruction == `DEBUG?1:0;
229 Bit#(1) dtmcontrol_sel = crossed_instruction == `DTMCONTROL?1:0;
230 Bit#(1) dmi_sel = crossed_instruction == `DMIACCESS?1:0;
231 Bit#(1) extest_select=crossed_instruction==`EXTEST?1:0;
232 Bit#(1) sample_preload_select=crossed_instruction==`SAMPLE_PRELOAD?1:0;
233
234 Bit#(1) instruction_tdo=crossed_instruction_shiftreg[0];
235 Bit#(1) bypass_tdo=crossed_bypass_sr;
236 Bit#(1) scan_en_tdo=crossed_scan_en_sr;
237 Bit#(1) scan_mode_te_tdo=crossed_scan_mode_te_sr;
238 Bit#(1) full_scan_en_tdo=crossed_full_scan_en_sr;
239 Bit#(1) scan_out_1_tdo=crossed_scan_out_1_sr;
240 Bit#(1) scan_out_2_tdo=crossed_scan_out_2_sr;
241 Bit#(1) scan_out_3_tdo=crossed_scan_out_3_sr;
242 Bit#(1) scan_out_4_tdo=crossed_scan_out_4_sr;
243 Bit#(1) scan_out_5_tdo=crossed_scan_out_5_sr;
244 Bit#(1) idcode_tdo=crossed_idcode_sr[0];
245 Bit#(1) dtmcontrol_tdo=crossed_dtmcontrol_shiftreg[0];
246 Bit#(1) dmiaccess_tdo=crossed_dmiaccess_shiftreg[0][0];
247
248
249
250 /*== This rule implements the TAPs STATE MACHINE====== */
251 rule just_display;
252 `ifdef verbose $display($time,"\tTAPSTATE: ",fshow(tapstate),"\tINSTRUCTION: %h",instruction_shiftreg); `endif
253 endrule
254 rule tap_state_machine;
255 case(tapstate)
256 TestLogicReset: if(wr_tms==0) tapstate<=RunTestIdle;
257 RunTestIdle : if(wr_tms==1) tapstate <= SelectDRScan;
258 SelectDRScan : if(wr_tms==1) tapstate <= SelectIRScan;
259 else tapstate <= CaptureDR;
260 CaptureDR : if(wr_tms==0) tapstate <= ShiftDR;
261 else tapstate <= Exit1DR;
262 ShiftDR : if(wr_tms==1) tapstate <= Exit1DR;
263 Exit1DR : if(wr_tms==0) tapstate <= PauseDR;
264 else tapstate <= UpdateDR;
265 PauseDR : if(wr_tms==1) tapstate <= Exit2DR;
266 Exit2DR : if(wr_tms==1) tapstate <= UpdateDR;
267 else tapstate <= ShiftDR;
268 UpdateDR : if(wr_tms==1) tapstate <= SelectDRScan;
269 else tapstate <= RunTestIdle;
270 SelectIRScan : if(wr_tms==1) tapstate <= TestLogicReset;
271 else tapstate <= CaptureIR;
272 CaptureIR : if(wr_tms==0) tapstate <= ShiftIR;
273 else tapstate <= Exit1IR;
274 ShiftIR : if(wr_tms==1) tapstate <= Exit1IR;
275 Exit1IR : if(wr_tms==0) tapstate <= PauseIR;
276 else tapstate <= UpdateIR;
277 PauseIR : if(wr_tms==1) tapstate <= Exit2IR;
278 Exit2IR : if(wr_tms==1) tapstate <= UpdateIR;
279 else tapstate <= ShiftIR;
280 UpdateIR : if(wr_tms==1) tapstate <= SelectDRScan;
281 else tapstate <= RunTestIdle;
282 default : tapstate <= TestLogicReset;
283 endcase
284 endrule
285
286 rule dmireset_generated(wr_dmireset_generated);
287 `ifdef verbose $display($time,"\tDTM: Received DMIRESET"); `endif
288 dmiaccess_shiftreg[1][1:0]<='d0;
289 response_status<=0;
290 capture_repsonse_from_dm<=False;
291 endrule
292 rule dmihardreset_generated(wr_dmihardreset_generated);
293 request_to_DM.deq;
294 response_from_DM.deq;
295 capture_repsonse_from_dm<=False;
296 endrule
297
298 /*======= perform dtmcontrol shifts ======== */
299 rule shift_dtm;
300 case(tapstate)
301 TestLogicReset: dtmcontrol<={17'd0,idle,2'b0,abits,version};
302 CaptureDR: if(dtmcontrol_sel==1) dtmcontrol_shiftreg<=dtmcontrol;
303 ShiftDR: if(dtmcontrol_sel==1) dtmcontrol_shiftreg<={wr_tdi,dtmcontrol_shiftreg[31:1]};
304 UpdateDR: if(dtmcontrol_sel==1) dtmcontrol<=dtmcontrol_shiftreg;
305 endcase
306 endrule
307 /*========================================== */
308 /*======= perform dmiaccess shifts ======== */
309 rule shift_dmiaccess(!wr_dmihardreset_generated);
310 case(tapstate)
311 TestLogicReset: dmiaccess_shiftreg[0]<='d0;
312 CaptureDR: if(dmi_sel==1)
313 if(response_from_DM.notEmpty)begin
314 let x=response_from_DM.first[33:0];
315 `ifdef verbose $display($time,"\tDTM: Getting response: data %h op: %h",x[33:2],x[1:0]); `endif
316 x[1:0]=x[1:0]|response_status;// keeping the lower 2 bits sticky
317 dmiaccess_shiftreg[0][33:0]<=x;
318 response_status<=x[1:0];
319 response_from_DM.deq;
320 `ifdef verbose $display($time,"\tDTM: New DMIACCESS value: %h",x); `endif
321 capture_repsonse_from_dm<=False;
322 dmistat<=x[1:0];
323 end
324 else begin
325 if(capture_repsonse_from_dm)
326 response_status<=3;
327 `ifdef verbose $display($time,"\tDTM: RESPONSE NOT AVAILABLE. DMIACCESS: %h",dmiaccess_shiftreg[0]); `endif
328 end
329 ShiftDR: if(dmi_sel==1) dmiaccess_shiftreg[0]<={wr_tdi,dmiaccess_shiftreg[0][39:1]};
330 UpdateDR: if(dmi_sel==1)
331 if(request_to_DM.notFull && dmiaccess_shiftreg[0][1:0]!=0 && capture_repsonse_from_dm==False)begin
332 request_to_DM.enq(dmiaccess_shiftreg[0]);
333 dmiaccess_shiftreg[0][1:0]<='d3;
334 capture_repsonse_from_dm<=True;
335 `ifdef verbose $display($time,"\tDTM: Sending request to Debug: %h",dmiaccess_shiftreg[0]); `endif
336 end
337 else begin
338 `ifdef verbose $display($time,"\tDTM: REQUEST NOT SERVED capture: %b DMIACCESS: %h",capture_repsonse_from_dm,dmiaccess_shiftreg[0]); `endif
339 // dmistat<=3;
340 // response_from_DM.enq('d3);
341 end
342 endcase
343 endrule
344 /*========================================== */
345
346 /*== perform instruction register shifts === */
347 rule shift_reg;
348 case(tapstate)
349 CaptureIR: instruction_shiftreg<='b10101;
350 ShiftIR : instruction_shiftreg<= {wr_tdi,instruction_shiftreg[4:1]};
351 endcase
352 endrule
353 rule transfer_instruction_on_nedge; // TODO negedge here
354 case(crossed_tapstate)
355 TestLogicReset :instruction<=`IDCODE;
356 UpdateIR :instruction<=crossed_instruction_shiftreg;
357 endcase
358 endrule
359
360 /*==== Bypass Section === */
361 rule bypass_logic;
362 case(tapstate)
363 TestLogicReset: bypass_sr<=1'b0;
364 CaptureDR : if(bypass_sel==1) bypass_sr<=1'b0;
365 ShiftDR : if(bypass_sel==1) bypass_sr<=wr_tdi;
366 endcase
367 endrule
368
369 /*==== Boundary Scan Section === */
370 rule bs_logic;
371 case(tapstate)
372 TestLogicReset: bs_sr<=1'b0;
373 CaptureDR : begin
374 if(extest_select==1) begin
375 shiftBscan2Edge_sr <= 1'b0;
376 selectJtagInput_sr <= 1'b0;
377 selectJtagOutput_sr <= 1'b0;
378 updateBscan_sr <= 1'b0;
379 bs_sr<=1'b0;
380 end else if (sample_preload_select ==1) begin
381 shiftBscan2Edge_sr <= 1'b0;
382 selectJtagInput_sr <= 1'b0;
383 selectJtagOutput_sr <= 1'b0;
384 bs_sr<=1'b0;
385 end
386 end
387 ShiftDR : begin
388 if(extest_select==1) begin
389 shiftBscan2Edge_sr <= 1'b1;
390 selectJtagInput_sr <= 1'b0;
391 selectJtagOutput_sr <= 1'b0;
392 updateBscan_sr <= 1'b0;
393 bs_sr<=wr_tdi;
394 end else if (sample_preload_select ==1) begin
395 bs_sr<=wr_tdi;
396 shiftBscan2Edge_sr <= 1'b1;
397 end
398 end
399 UpdateDR : begin
400 if(extest_select==1) begin
401 shiftBscan2Edge_sr <= 1'b1;
402 selectJtagInput_sr <= 1'b1;
403 selectJtagOutput_sr <= 1'b1;
404 updateBscan_sr <= 1'b1;
405 end
406 end
407 endcase
408 endrule
409
410 /*==== Scan Chain Section === */
411 rule scan_logic;
412 case(tapstate)
413 TestLogicReset: begin
414 scan_en_sr<=1'b0;
415 scan_mode_te_sr<=1'b0;
416 scan1_sr<=1'b0;
417 scan2_sr<=1'b0;
418 scan3_sr<=1'b0;
419 scan4_sr<=1'b0;
420 scan5_sr<=1'b0;
421 scanall_sr<=1'b0;
422 full_scan_en_sr<=1'b0;
423 wr_scan_shift_en[0]<=1'b0;
424 end
425 CaptureDR : begin
426 if(scan_en_sel==1) scan_en_sr<=1'b0;
427 else if(scan_mode_te_sel==1) scan_mode_te_sr<=1'b0;
428 else if(scan1_sel==1) scan1_sr<=1'b0;
429 else if(scan2_sel==1) scan2_sr<=1'b0;
430 else if(scan3_sel==1) scan3_sr<=1'b0;
431 else if(scan4_sel==1) scan4_sr<=1'b0;
432 else if(scan5_sel==1) scan5_sr<=1'b0;
433 else if(scanall_sel==1) scanall_sr<=1'b0;
434 else if(full_scan_en_sel==1) full_scan_en_sr<=1'b0;
435 wr_scan_shift_en[0]<=1'b0;
436 end
437 ShiftDR : begin
438 if(scan_en_sel==1) scan_en_sr<=wr_tdi;
439 else if(scan_mode_te_sel==1) scan_mode_te_sr<=wr_tdi;
440 else if(scan1_sel==1) scan1_sr<=wr_tdi;
441 else if(scan2_sel==1) scan2_sr<=wr_tdi;
442 else if(scan3_sel==1) scan3_sr<=wr_tdi;
443 else if(scan4_sel==1) scan4_sr<=wr_tdi;
444 else if(scan5_sel==1) scan5_sr<=wr_tdi;
445 else if(scanall_sel==1) scanall_sr<=wr_tdi;
446 else if(full_scan_en_sel==1) full_scan_en_sr<=wr_tdi;
447 if ((scan1_sel == 1'b1 || scan2_sel == 1'b1|| scan3_sel == 1'b1|| scan4_sel == 1'b1|| scan5_sel == 1'b1|| scanall_sel == 1'b1) || (scan_en_sel == 1'b1 && wr_tdi == 1'b0)) wr_scan_shift_en[1] <=1'b1;
448 end
449 UpdateDR : wr_scan_shift_en[0] <=1'b0;
450 endcase
451 endrule
452
453 rule full_scan_mux_logic;
454 if (full_scan_en_sr == 1'b1) begin
455 wr_scan_in_1_all <= scanall_sr;
456 wr_scan_in_2_out1 <= scan_out_1_sr;
457 wr_scan_in_3_out2 <= scan_out_2_sr;
458 wr_scan_in_4_out3 <= scan_out_3_sr;
459 wr_scan_in_5_out4 <= scan_out_4_sr;
460 end
461 else begin
462 wr_scan_in_1_all <= scan1_sr;
463 wr_scan_in_2_out1 <= scan2_sr;
464 wr_scan_in_3_out2 <= scan3_sr;
465 wr_scan_in_4_out3 <= scan4_sr;
466 wr_scan_in_5_out4 <= scan5_sr;
467 end
468 endrule
469
470 /*======= IDCODE section === */
471 rule idcode_logic;
472 case(tapstate)
473 TestLogicReset:idcode_sr<=`IDCODEVALUE;
474 CaptureDR: if(idcode_sel==1) idcode_sr<=`IDCODEVALUE;
475 ShiftDR : if(idcode_sel==1) idcode_sr<={wr_tdi,idcode_sr[31:1]};
476 endcase
477 endrule
478
479 rule generate_tdo_outputpin;
480 if(crossed_tapstate==ShiftIR)
481 rg_tdo<=instruction_tdo;
482 else
483 case(instruction)
484 `IDCODE: rg_tdo<=idcode_tdo;
485 `DEBUG : rg_tdo<=crossed_debug_tdi;
486 `EXTEST: rg_tdo<=crossed_bs_chain_tdo;
487 `SAMPLE_PRELOAD: rg_tdo<=crossed_bs_chain_tdo;
488 `BYPASS: rg_tdo<=bypass_tdo;
489 `SCANEN: rg_tdo<=scan_en_tdo;
490 `SCANMODE_TE: rg_tdo<=scan_mode_te_tdo;
491 `FULLSCANEN: rg_tdo<=full_scan_en_tdo;
492 `SCAN1: rg_tdo <= scan_out_1_tdo;
493 `SCAN2: rg_tdo <= scan_out_2_tdo;
494 `SCAN3: rg_tdo <= scan_out_3_tdo;
495 `SCAN4: rg_tdo <= scan_out_4_tdo;
496 `SCAN5: rg_tdo <= scan_out_5_tdo;
497 `SCANALL: rg_tdo <= scan_out_5_tdo;
498 `DTMCONTROL: rg_tdo<=dtmcontrol_tdo;
499 `DMIACCESS: rg_tdo<=dmiaccess_tdo;
500 default: rg_tdo<=bypass_tdo;
501 endcase
502 endrule
503
504 /*======== SCAN input (scan chain outputs) pins ===== */
505 method Action scan_out_1_i(Bit#(1) scan_out_1);
506 scan_out_1_sr<=scan_out_1;
507 endmethod
508 method Action scan_out_2_i(Bit#(1) scan_out_2);
509 scan_out_2_sr<=scan_out_2;
510 endmethod
511 method Action scan_out_3_i(Bit#(1) scan_out_3);
512 scan_out_3_sr<=scan_out_3;
513 endmethod
514 method Action scan_out_4_i(Bit#(1) scan_out_4);
515 scan_out_4_sr<=scan_out_4;
516 endmethod
517 method Action scan_out_5_i(Bit#(1) scan_out_5);
518 scan_out_5_sr<=scan_out_5;
519 endmethod
520 /*======== JTAG input pins ===== */
521
522 interface tms = interface Put
523 method Action put(Bit#(1) in);
524 wr_tms<=in;
525 endmethod
526 endinterface;
527
528 interface tdi = interface Put
529 method Action put(Bit#(1) in);
530 wr_tdi<=in;
531 endmethod
532 endinterface;
533
534 /*============================= */
535 method Action debug_tdi_i(Bit#(1) debug_tdi);
536 wr_debug_tdi<=debug_tdi;
537 endmethod
538 /*======= Boundary Scan Input Pins ====== */
539 method Action bs_chain_i(Bit#(1) bs_chain);
540 wr_bs_chain_tdo<=bs_chain;
541 endmethod
542 /*======== TAP States ============= */
543 method shift_dr=tapstate==ShiftDR?1:0;
544 method pause_dr=tapstate==PauseDR?1:0;
545 method update_dr=tapstate==UpdateDR?1:0;
546 method capture_dr=tapstate==CaptureDR?1:0;
547 /*=================================== */
548 method debug_select =crossed_instruction==`DEBUG?1:0;
549 /*================================ */
550 /*======= SCAN Output (Scan Chain Inputs) Pins ====== */
551 method scan_in_1 = wr_scan_in_1_all;
552 method scan_in_2 = wr_scan_in_2_out1;
553 method scan_in_3 = wr_scan_in_3_out2;
554 method scan_in_4 = wr_scan_in_4_out3;
555 method scan_in_5 = wr_scan_in_5_out4;
556 method scan_en = scan_en_sr;
557 method scan_mode_te = scan_mode_te_sr;
558 /*======= Boundary Scan Output Pins ====== */
559 method shiftBscan2Edge = shiftBscan2Edge_sr;
560 method selectJtagInput = selectJtagInput_sr;
561 method selectJtagOutput = selectJtagOutput_sr;
562 method updateBscan = updateBscan_sr;
563 method bscan_in = bs_sr;
564 method scan_shift_en = wr_scan_shift_en[1];
565 /*======= JTAG Output Pins ====== */
566 interface tck = interface Get
567 method ActionValue#(Bit#(1)) get;
568 return 'b1; //#def_clk;
569 endmethod
570 endinterface;
571
572 interface tdo = interface Get
573 method ActionValue#(Bit#(1)) get;
574 return crossed_output_tdo;
575 endmethod
576 endinterface;
577
578 method debug_tdo = wr_tdi;
579 method Bit#(1) tdo_oe = ((tapstate == ShiftIR) || (tapstate == ShiftDR))?1:0;
580 method Action response_from_dm(Bit#(34) responsedm) if(response_from_DM.notFull);
581 if(capture_repsonse_from_dm)
582 response_from_DM.enq(responsedm);
583 endmethod
584 method ActionValue#(Bit#(40)) request_to_dm if(request_to_DM.notEmpty);
585 request_to_DM.deq;
586 return request_to_DM.first;
587 endmethod
588 endmodule
589
590 endpackage
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