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add emmc dummy class
[shakti-peripherals.git] / src / peripherals / sdram / sdr_top.bsv
1 /*
2 Copyright (c) 2013, IIT Madras
3 All rights reserved.
4
5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
6
7 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
8 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
9 * Neither the name of IIT Madras nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
10
11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
13 */
14
15 `include "instance_defines.bsv"
16 `define DELAY 250
17 `define SDR_RFSH_TIMER_W 12
18 `define SDR_RFSH_ROW_CNT_W 3
19
20 `define ACTPRE_DELAY 8'h0
21 `define PREACT_DELAY 8'h8
22 `define ACT_RW_DELAY 8'h10
23 `define EN_SDRAM 8'h18
24 `define MAX_REQ 8'h20
25 `define MODE_REG 8'h28
26 `define CAS_LATNCY 8'h30
27 `define AUTO_REFRESH 8'h38
28 `define RECRY_DELAY 8'h40
29 `define RFRSH_TIMER 8'h48
30 `define RFRSH_ROW_CNT 8'h50
31 `define SDR_INIT_DONE 8'h58
32 `define SDR_WIDTH 8'h60
33 `define SDR_COLBITS 8'h68
34 `define SDR_CLK_DELAY 8'h78
35 `define verbose
36
37 package sdr_top;
38
39 import GetPut:: *;
40 import Semi_FIFOF :: *;
41 import AXI4_Types :: *;
42 import AXI4_Fabric :: *;
43 import bsvmksdrc_top :: *;
44 import BUtils ::*;
45 import Connectable ::*;
46 import ConfigReg ::*;
47 import DReg::*;
48 import FIFOF::*;
49 import Clocks::*;
50
51 interface Ifc_sdram_out;
52 (*always_enabled, always_ready*)
53 interface Put#(Bit#(64)) ipad_sdr_din;
54 interface Get#(Bit#(64)) osdr_dout;
55 interface Get#(Bit#(64)) osdr_den_n;
56 interface Get#(Bit#(1)) osdr_cke;
57 interface Get#(Bit#(1)) osdr_cs_n;
58 interface Get#(Bit#(1)) osdr_ras_n;
59 interface Get#(Bit#(1)) osdr_cas_n;
60 interface Get#(Bit#(1)) osdr_we_n;
61 interface Get#(Bit#(8)) osdr_dqm;
62 interface Get#(Bit#(2)) osdr_ba;
63 interface Get#(Bit#(13)) osdr_addr;
64 interface Get#(Bit#(1)) osdr_clock;
65
66 endinterface
67
68 interface Ifc_sdr_slave;
69 interface AXI4_Slave_IFC#(`PADDR, `Reg_width,`USERSPACE) axi4_slave_sdram;
70 interface AXI4_Slave_IFC#(`PADDR, `Reg_width,`USERSPACE) axi4_slave_cntrl_reg;
71 interface Ifc_sdram_out ifc_sdram_out;
72 endinterface
73
74 typedef enum{
75 IDLE,
76 WRITE_START,
77 WAIT_DELAY,
78 WRITE_FIRST,
79 WRITE_DATA0,
80 WRITE_DATA1
81 } Write_state deriving(Bits, Eq, FShow);
82
83 typedef enum{
84 IDLE,
85 START_READ,
86 READ_DATA,
87 READ_FLUSH
88 } Read_state deriving(Bits, Eq,FShow);
89
90 typedef enum {
91 IDLE,
92 START_SPLIT,
93 SEND_VALUE
94 } Write_split_states deriving(Bits, Eq, FShow);
95
96
97
98 function (Bit#(9)) fn_wr_len(Bit#(8) length, Bit#(3) awsize, Bit#(3) lwr_addr);
99 Bit#(3) w_packet = 0;
100 Bit#(9) s_length = 0;
101 case(awsize)
102
103 'd0 : begin
104 w_packet = lwr_addr >> awsize;
105 s_length = ((zeroExtend(length) + zeroExtend(w_packet)) >> 3) + 1;
106 end
107 'd1: begin
108 w_packet = lwr_addr >> awsize;
109 s_length = ((zeroExtend(length) + zeroExtend(w_packet)) >> 2) + 1;
110 //`ifdef verbose $display($time(),"\t SSSS w_packet %b s_lenght %h length %h", w_packet, s_length, length); `endif
111 end
112 'd2 : begin
113 //w_packet = lwr_addr >> awsize;
114 // s_length = ((s_length + w_packets) >> 1) + 1;
115 s_length = zeroExtend(length >> 1) + 1;
116 end
117 'd3 : begin
118 s_length = zeroExtend(length) + 1;
119 end
120 endcase
121
122 return s_length;
123 endfunction
124
125
126 function Bit#(64) fn_wr_split_data(Bit#(64) data, Bit#(8) wstrb);
127 Bit#(64) data0 = 0;
128 if(wstrb[0] == 1)
129 data0[7:0] = data[7:0];
130 else
131 data0[7:0] = 0;
132
133 if(wstrb[1] == 1)
134 data0[15:8] = data[15:8];
135 else
136 data0[15:8] = 0;
137
138 if(wstrb[2] == 1)
139 data0[23:16] = data[23:16];
140 else
141 data0[23:16] = 0;
142
143 if(wstrb[3] == 1)
144 data0[31:24] = data[31:24];
145 else
146 data0[31:24] = 0;
147
148 if(wstrb[4] == 1)
149 data0[39:32] = data[39:32];
150 else
151 data0[39:32] = 0;
152
153 if(wstrb[5] == 1)
154 data0[47:40] = data[47:40];
155 else
156 data0[47:40] = 0;
157
158 if(wstrb[6] == 1)
159 data0[55:48] = data[55:48];
160 else
161 data0[55:48] = 0;
162
163 if(wstrb[7] == 1)
164 data0[63:56] = data[63:56];
165 else
166 data0[63:56] = 0;
167
168 return data0;
169 endfunction
170
171 function Bit#(26) fn_wr_address(Bit#(`PADDR) address);
172 Bit#(29) sdr_addr = address[31:3];
173 return sdr_addr[25:0];
174 endfunction
175
176 function Bit#(64) fn_rd_data(Bit#(3) bsize,Bit#(4) lwr_addr,Bit#(64) data);
177
178 case(bsize)
179 'b000: begin
180 case(lwr_addr)
181 'b000: begin
182 return duplicate(data[7:0]);
183 end
184 'b001: begin
185 return duplicate(data[15:8]);
186 end
187 'b010: begin
188 return duplicate(data[23:16]);
189 end
190 'b011: begin
191 return duplicate(data[31:24]);
192 end
193 'b100: begin
194 return duplicate(data[39:32]);
195 end
196 'b101: begin
197 return duplicate(data[47:40]);
198 end
199 'b110: begin
200 return duplicate(data[55:48]);
201 end
202 'b111: begin
203 return duplicate(data[63:56]);
204 end
205 endcase
206 end
207
208 'b001: begin
209 case(lwr_addr)
210 'b000: begin
211 return duplicate(data[15:0]);
212 end
213 'b010: begin
214 return duplicate(data[31:16]);
215 end
216 'b100: begin
217 return duplicate(data[47:32]);
218 end
219 'b110: begin
220 return duplicate(data[63:48]);
221 end
222 endcase
223 end
224
225 'b010: begin
226 case(lwr_addr)
227 'b000: begin
228 return duplicate(data[31:0]);
229 end
230 'b100: begin
231 return duplicate(data[63:32]);
232 end
233 endcase
234 end
235
236 'b011: begin
237 return data;
238 end
239 endcase
240 endfunction
241
242
243
244
245
246 (*synthesize*)
247
248 module mksdr_axi4_slave#(Clock clk0, Reset rst0) (Ifc_sdr_slave);
249
250 Reg#(Bit#(9)) rg_delay_count <- mkReg(0,clocked_by clk0, reset_by rst0);
251 Reg#(Bit#(9)) rg_rd_actual_len <- mkReg(0,clocked_by clk0, reset_by rst0);
252 Reg#(bit) rg_app_req <- mkDReg(0,clocked_by clk0, reset_by rst0);
253 Reg#(bit) rg_app_req_wrap <- mkConfigReg(0,clocked_by clk0, reset_by rst0);
254 Reg#(Bit#(26)) rg_app_req_addr <- mkConfigReg(0,clocked_by clk0, reset_by rst0);
255 Reg#(Bit#(4)) rg_cfg_sdr_tras_d <- mkConfigReg(4'h4,clocked_by clk0, reset_by rst0);
256 Reg#(Bit#(4)) rg_cfg_sdr_trp_d <- mkConfigReg(4'h2,clocked_by clk0, reset_by rst0);
257 Reg#(Bit#(4)) rg_cfg_sdr_trcd_d <- mkConfigReg(4'h2,clocked_by clk0, reset_by rst0);
258 Reg#(bit) rg_cfg_sdr_en <- mkConfigReg(1'h0,clocked_by clk0, reset_by rst0);
259 Reg#(Bit#(2)) rg_cfg_req_depth <- mkConfigReg(2'h3,clocked_by clk0, reset_by rst0);
260 Reg#(Bit#(13)) rg_cfg_sdr_mode_reg <- mkConfigReg(13'h032,clocked_by clk0, reset_by rst0);
261 Reg#(Bit#(3)) rg_cfg_sdr_cas <- mkConfigReg(3'h3,clocked_by clk0, reset_by rst0);
262 Reg#(Bit#(4)) rg_cfg_sdr_trcar_d <- mkConfigReg(4'h7,clocked_by clk0, reset_by rst0);
263 Reg#(Bit#(4)) rg_cfg_sdr_twr_d <- mkConfigReg(4'h1,clocked_by clk0, reset_by rst0);
264 Reg#(Bit#(2)) rg_cfg_sdr_width <- mkConfigReg(2'b0,clocked_by clk0, reset_by rst0);
265 Reg#(Bit#(2)) rg_cfg_colbits <- mkConfigReg(2'b01,clocked_by clk0, reset_by rst0);
266 Reg#(Bit#(8)) rg_cfg_sdr_clk_delay <- mkConfigReg(8'b00001000,clocked_by clk0, reset_by rst0);
267
268 Reg#(Bit#(`SDR_RFSH_TIMER_W )) rg_cfg_sdr_rfsh <- mkConfigReg(12'h100,clocked_by clk0, reset_by rst0);
269 Reg#(Bit#(`SDR_RFSH_ROW_CNT_W)) rg_cfg_sdr_rfmax <- mkConfigReg(3'h6,clocked_by clk0, reset_by rst0);
270 Reg#(Bit#(9)) rg_app_req_len <- mkConfigReg(0,clocked_by clk0, reset_by rst0);
271 Reg#(Bit#(4)) rg_lwraddr <- mkConfigReg(0,clocked_by clk0, reset_by rst0);
272 Reg#(Bit#(3)) rg_arsize <- mkConfigReg(0,clocked_by clk0, reset_by rst0);
273 Reg#(bit) rg_app_req_wr_n <- mkConfigReg(0,clocked_by clk0, reset_by rst0);
274 Reg#(Bit#(8)) rg_app_wr_en_n <- mkDWire(8'hFF,clocked_by clk0, reset_by rst0);
275 Reg#(Bit#(64)) rg_app_wr_data <- mkDWire(0,clocked_by clk0, reset_by rst0);
276 Wire#(Bool) wr_sdr_init_done <- mkDWire(False,clocked_by clk0, reset_by rst0);
277 Wire#(Bool) wr_app_req_ack <- mkDWire(False,clocked_by clk0, reset_by rst0);
278 Wire#(Bool) wr_app_wr_next_req <- mkDWire(False,clocked_by clk0, reset_by rst0);
279 Wire#(Bool) wr_app_rd_valid <- mkDWire(False,clocked_by clk0, reset_by rst0);
280 Wire#(Bool) wr_app_last_rd <- mkDWire(False,clocked_by clk0, reset_by rst0);
281 Wire#(Bool) wr_app_last_wr <- mkDWire(False,clocked_by clk0, reset_by rst0);
282 Wire#(Bit#(64)) wr_app_rd_data <- mkWire(clocked_by clk0, reset_by rst0);
283
284
285 Reg#(Bit#(4)) rg_rid <- mkReg(0, clocked_by clk0, reset_by rst0);
286 Reg#(bit) rg_rd_not_active_flag <- mkSyncRegToCC(0,clk0, rst0);
287 Reg#(Bit#(4)) rg_ctrl_rid <- mkReg(0);
288 Reg#(Bit#(4)) rg_wid <- mkReg(0);
289
290 Reg#(Write_split_states) rg_wr_split_states <- mkReg(IDLE);
291 Reg#(Bit#(3)) rg_awsize <- mkReg(0);
292 Reg#(Bit#(9)) rg_ac_count <- mkReg(0);
293 Reg#(Bit#(6)) rg_single_burst <- mkReg(0);
294 Reg#(Bit#(64)) rg_wr_ac_data <- mkReg(0);
295 Reg#(Bit#(8)) rg_wr_ac_wstrb <- mkReg(0);
296 Reg#(Bit#(4)) rg_wr_lwr_addr <- mkReg(0);
297 Reg#(Bit#(9)) rg_local_actual_wr_length <- mkReg(0);
298 Reg#(Bit#(9)) rg_actual_wr_length <- mkSyncRegFromCC(0,clk0);
299 Reg#(Bit#(32)) rg_wr_address <- mkSyncRegFromCC(0,clk0);
300
301 Reg#(Bit#(3)) rg_awsize_sclk <- mkSyncRegFromCC(0,clk0);
302
303 Reg#(Bit#(9)) rg_burst_counter <- mkReg(0);
304
305 Bool burst_eq = (rg_burst_counter == rg_local_actual_wr_length);
306
307 Reg#(Bit#(3)) rg_packets <- mkReg(0);
308 Reg#(Bit#(3)) rg_packet_counter <- mkReg(0);
309
310
311 Reg#(Write_state) rg_write_states <- mkReg(IDLE,clocked_by clk0, reset_by rst0);
312 Reg#(Read_state) rg_read_states <- mkReg(IDLE,clocked_by clk0, reset_by rst0);
313
314 FIFOF#(AXI4_Wr_Addr#(`PADDR,`USERSPACE)) ff_wr_addr <- mkSizedFIFOF(13);
315 FIFOF#(AXI4_Wr_Data#(`Reg_width)) ff_wr_data <- mkSizedFIFOF(13);
316 SyncFIFOIfc#(Bit#(`Reg_width)) ff_ac_wr_data <- mkSyncFIFOFromCC(13,clk0);
317 SyncFIFOIfc#(Bit#(8)) ff_ac_wr_wstrb <- mkSyncFIFOFromCC(13,clk0);
318
319 SyncFIFOIfc#(Bool) ff_sync_write_response<-mkSyncFIFOToCC(1,clk0,rst0);
320
321 //FIFOF#(AXI4_Rd_Addr#(`PADDR,`USERSPACE)) ff_rd_addr <- mkSizedFIFOF(3);
322 FIFOF#(Bit#(64)) ff_rd_data <- mkSizedFIFOF(86,clocked_by clk0, reset_by rst0);
323 SyncFIFOIfc#(AXI4_Rd_Addr#(`PADDR,`USERSPACE)) ff_rd_addr <- mkSyncFIFOFromCC(30,clk0);
324 SyncFIFOIfc#(AXI4_Rd_Data#(`Reg_width,`USERSPACE)) ff_sync_read_response <-mkSyncFIFOToCC(13,clk0,rst0);
325
326 SyncFIFOIfc#(Tuple2#(Bit#(`PADDR),Bit#(`Reg_width))) ff_sync_ctrl_write<- mkSyncFIFOFromCC(1,clk0);
327 SyncFIFOIfc#(Bit#(`PADDR)) ff_sync_ctrl_read<- mkSyncFIFOFromCC(1,clk0);
328 SyncFIFOIfc#(Bit#(`Reg_width)) ff_sync_ctrl_read_response<- mkSyncFIFOToCC(1,clk0,rst0);
329
330 // Polling Registers
331 Reg#(Bit#(2)) rg_poll_cnt <- mkReg(0,clocked_by clk0, reset_by rst0);
332 Reg#(Bool) rg_polling_status <- mkSyncRegToCC(False,clk0,rst0);
333 Reg#(Bool) rg_polling_status_clk0 <- mkReg(False,clocked_by clk0, reset_by rst0);
334 Reg#(Bool) rg_rd_trnc_flg <- mkReg(False);
335 Reg#(Bool) rg_wr_trnc_flg <- mkReg(False);
336 Reg#(bit) rg_odd_len <- mkReg(0);
337
338 AXI4_Slave_Xactor_IFC #(`PADDR, `Reg_width, `USERSPACE) s_xactor_sdram <- mkAXI4_Slave_Xactor;
339 AXI4_Slave_Xactor_IFC #(`PADDR, `Reg_width, `USERSPACE) s_xactor_cntrl_reg <- mkAXI4_Slave_Xactor;
340 Ifc_sdram sdr_cntrl <- mksdrc_top(clocked_by clk0, reset_by rst0);
341
342 // TODO remove the following when clock to bit type conversion is done
343 Reg#(Bit#(1)) rg_dummy <- mkReg(0, clocked_by clk0, reset_by rst0);
344
345 function Action fn_wr_cntrl_reg(Bit#(64) data, Bit#(8) address);
346 action
347 case(address)
348
349 `ACTPRE_DELAY : rg_cfg_sdr_tras_d <= data[3:0];
350
351 `PREACT_DELAY : rg_cfg_sdr_trp_d <= data[3:0];
352
353 `ACT_RW_DELAY : rg_cfg_sdr_trcd_d <= data[3:0];
354
355 `EN_SDRAM : rg_cfg_sdr_en <= data[0];
356
357 `MAX_REQ : rg_cfg_req_depth <= data[1:0];
358
359 `MODE_REG : rg_cfg_sdr_mode_reg <= data[12:0];
360
361 `CAS_LATNCY : rg_cfg_sdr_cas <= data[2:0];
362
363 `AUTO_REFRESH : rg_cfg_sdr_trcar_d <= data[3:0];
364
365 `RECRY_DELAY : rg_cfg_sdr_twr_d <= data[3:0];
366
367 `RFRSH_TIMER : rg_cfg_sdr_rfsh <= data[11:0];
368
369 `RFRSH_ROW_CNT : rg_cfg_sdr_rfmax <= data[2:0];
370
371 `SDR_WIDTH : rg_cfg_sdr_width <= data [1:0];
372
373 `SDR_COLBITS : rg_cfg_colbits <= data [1:0];
374
375
376 `SDR_CLK_DELAY : rg_cfg_sdr_clk_delay <= data [7:0];
377
378 default : noAction;
379 endcase
380 endaction
381 endfunction
382
383
384 function Bit#(64) fn_rd_cntrl_reg(Bit#(8) address);
385 case(address)
386
387 `ACTPRE_DELAY : return extend(rg_cfg_sdr_tras_d);
388
389 `PREACT_DELAY : return extend(rg_cfg_sdr_trp_d);
390
391 `ACT_RW_DELAY : return extend(rg_cfg_sdr_trcd_d);
392
393 `EN_SDRAM : return extend(rg_cfg_sdr_en);
394
395 `MAX_REQ : return extend(rg_cfg_req_depth);
396
397 `MODE_REG : return extend(rg_cfg_sdr_mode_reg);
398
399 `CAS_LATNCY : return extend(rg_cfg_sdr_cas);
400
401 `AUTO_REFRESH : return extend(rg_cfg_sdr_trcar_d);
402
403 `RECRY_DELAY : return extend(rg_cfg_sdr_twr_d);
404
405 `RFRSH_TIMER : return extend(rg_cfg_sdr_rfsh);
406
407 `RFRSH_ROW_CNT : return extend(rg_cfg_sdr_rfmax);
408
409 `SDR_INIT_DONE : return extend(pack(wr_sdr_init_done));
410
411 `SDR_WIDTH : return extend(rg_cfg_sdr_width);
412
413 `SDR_COLBITS : return extend(rg_cfg_colbits);
414
415
416 `SDR_CLK_DELAY : return extend(rg_cfg_sdr_clk_delay);
417
418 endcase
419 endfunction
420
421 //(*preempts="(rl_pop_read_request, rl_send_rd_data, rl_send_read_data, rl_flush_redundant_data), rl_write_transaction_write_start"*)
422
423 rule rl_for_writing_ctrl_reg(ff_sync_ctrl_write.notFull);
424 let aw <- pop_o(s_xactor_cntrl_reg.o_wr_addr);
425 let w <- pop_o(s_xactor_cntrl_reg.o_wr_data);
426 `ifdef verbose $display($time,"\tSDRAM: control_reg written addr %x data %x", aw.awaddr, w.wdata); `endif
427 ff_sync_ctrl_write.enq(tuple2(aw.awaddr,w.wdata));
428 let w_resp = AXI4_Wr_Resp {bresp: AXI4_OKAY, buser: 0, bid: aw.awid};
429 s_xactor_cntrl_reg.i_wr_resp.enq(w_resp);
430 endrule
431
432 rule rl_perform_write_to_ctrl(ff_sync_ctrl_write.notEmpty);
433 let {awaddr,wdata}=ff_sync_ctrl_write.first;
434 `ifdef verbose $display("\tSDRAM: "); `endif
435 ff_sync_ctrl_write.deq;
436 `ifdef verbose $display($time,"\tSDRAM: Actually writing data: %h to addr: %h", wdata, awaddr); `endif
437 fn_wr_cntrl_reg(wdata , truncate(awaddr));
438 endrule
439
440 rule rl_for_read_cntrl_reg;
441 let ar <- pop_o(s_xactor_cntrl_reg.o_rd_addr);
442 ff_sync_ctrl_read.enq(ar.araddr);
443 rg_ctrl_rid<=ar.arid;
444 endrule
445
446 rule rl_send_ctrl_read_response(ff_sync_ctrl_read.notEmpty);
447 ff_sync_ctrl_read_response.enq(fn_rd_cntrl_reg(truncate(ff_sync_ctrl_read.first)));
448 ff_sync_ctrl_read.deq;
449 endrule
450
451 rule sync_ctr_response(ff_sync_ctrl_read_response.notEmpty);
452 ff_sync_ctrl_read_response.deq;
453 let r = AXI4_Rd_Data {rresp: AXI4_OKAY, rdata:ff_sync_ctrl_read_response.first , rlast: True, ruser: 0, rid: rg_ctrl_rid};
454 s_xactor_cntrl_reg.i_rd_data.enq(r);
455 endrule
456
457 rule rl_direct_connection_insdram;
458 sdr_cntrl.iapp_req(rg_app_req);
459 sdr_cntrl.iapp_req_wrap(rg_app_req_wrap);
460 sdr_cntrl.iapp_req_addr(rg_app_req_addr);
461 sdr_cntrl.iapp_req_len(rg_app_req_len);
462 sdr_cntrl.iapp_req_wr_n(rg_app_req_wr_n);
463 sdr_cntrl.iapp_wr_data(rg_app_wr_data);
464 sdr_cntrl.iapp_wr_en_n(rg_app_wr_en_n);
465 endrule
466
467 rule rl_direct_connection_outsdram;
468 wr_sdr_init_done <= sdr_cntrl.osdr_init_done ;
469 wr_app_req_ack <= sdr_cntrl.oapp_req_ack ();
470 wr_app_wr_next_req <= sdr_cntrl.oapp_wr_next_req ();
471 wr_app_rd_valid <= sdr_cntrl.oapp_rd_valid ();
472 wr_app_last_rd <= sdr_cntrl.oapp_last_rd ();
473 wr_app_last_wr <= sdr_cntrl.oapp_last_wr ();
474 wr_app_rd_data <= sdr_cntrl.oapp_rd_data ();
475 endrule
476
477 rule rl_direct_connection_config_reg;
478 sdr_cntrl.icfg_sdr_tras_d(rg_cfg_sdr_tras_d);
479 sdr_cntrl.icfg_sdr_trp_d(rg_cfg_sdr_trp_d);
480 sdr_cntrl.icfg_sdr_trcd_d(rg_cfg_sdr_trcd_d);
481 sdr_cntrl.icfg_sdr_en(rg_cfg_sdr_en);
482 sdr_cntrl.icfg_req_depth(rg_cfg_req_depth);
483 sdr_cntrl.icfg_sdr_mode_reg(rg_cfg_sdr_mode_reg);
484 sdr_cntrl.icfg_sdr_cas(rg_cfg_sdr_cas);
485 sdr_cntrl.icfg_sdr_trcar_d(rg_cfg_sdr_trcar_d);
486 sdr_cntrl.icfg_sdr_twr_d(rg_cfg_sdr_twr_d);
487 sdr_cntrl.icfg_sdr_rfsh(rg_cfg_sdr_rfsh);
488 sdr_cntrl.icfg_sdr_rfmax(rg_cfg_sdr_rfmax);
489 sdr_cntrl.icfg_sdr_width(rg_cfg_sdr_width);
490 sdr_cntrl.icfg_colbits(rg_cfg_colbits);
491 endrule
492
493 rule rl_intial_polling(rg_polling_status_clk0 == False && wr_sdr_init_done == True);
494 `ifdef verbose $display($time,"\tSDRAM: POLLING MODE: %d",rg_poll_cnt); `endif
495 case (rg_poll_cnt)
496 0: begin
497 rg_app_req <= 1;
498 rg_app_req_addr <= 0;
499 rg_app_req_len <= 1;
500 rg_app_req_wr_n <= 0;
501 rg_app_wr_en_n <= 'hFF;
502 rg_app_wr_data <= 0;
503 rg_poll_cnt <= rg_poll_cnt + 1;
504 end
505 1: begin
506 rg_app_req <= 1;
507 rg_app_req_addr <= 0;
508 rg_app_req_len <= 1;
509 rg_app_req_wr_n <= 0;
510 rg_app_wr_en_n <= 'hFF;
511 rg_app_wr_data <= 0;
512 rg_poll_cnt <= rg_poll_cnt + 1;
513 end
514 2: begin
515 rg_app_req <= 0;
516 rg_app_req_addr <= 0;
517 rg_app_wr_en_n <= 'hFF;
518 rg_app_wr_data <= 0;
519 if(wr_app_wr_next_req == True)
520 rg_poll_cnt <= rg_poll_cnt + 1;
521 end
522 3: begin
523 rg_polling_status <= True;
524 rg_polling_status_clk0<=True;
525 end
526 endcase
527 endrule
528
529 /******************* WRITE TRANSACTION ****************/
530
531 rule rl_parallel_data_enq(rg_polling_status == True && rg_rd_trnc_flg == False);
532 let aw <- pop_o(s_xactor_sdram.o_wr_addr);
533 let w <- pop_o(s_xactor_sdram.o_wr_data);
534 ff_wr_addr.enq(aw);
535 ff_wr_data.enq(w);
536 rg_wr_trnc_flg <= True;
537 `ifdef verbose $display($time,"\tSDRAM: WRITE_FIRST Parallel enq %h addr: %h",w.wdata,aw.awaddr); `endif
538 endrule
539
540 rule rl_write_split_state(rg_wr_split_states == IDLE);
541 let aw = ff_wr_addr.first();
542 if(aw.awsize != 3) begin
543 rg_actual_wr_length <= fn_wr_len(aw.awlen, aw.awsize, aw.awaddr[2:0]);
544
545 rg_local_actual_wr_length <= extend(aw.awlen);
546 end
547 else begin
548 rg_actual_wr_length <= extend(aw.awlen) + 1;
549 rg_local_actual_wr_length <= extend(aw.awlen);
550 end
551 rg_wid <= aw.awid;
552 rg_awsize <= aw.awsize;
553 rg_awsize_sclk <= aw.awsize;
554 rg_wr_address <= aw.awaddr;
555 rg_wr_lwr_addr <= extend(aw.awaddr[2:0]);
556 rg_wr_split_states <= START_SPLIT;
557 rg_packets <= (aw.awsize==0)?7:(aw.awsize==1)?3:(aw.awsize == 2)? 1 : (aw.awsize == 3) ? 0 : 0; //(64 >> (aw.awsize+4)); //1 << ~aw.awsize[1:0];
558 rg_packet_counter <= (aw.awaddr[2:0]) >> aw.awsize;
559 `ifdef verbose $display($time,"Initial Values -- Starting IDLE to START_SPLIT"); `endif
560 //$display("Initial Values: rg_packets: %h rg_packet_counter: %h ",(64>>(aw.awsize+4)),aw.awaddr[2:0]>>aw.awsize);
561 rg_burst_counter <= 0;
562 endrule
563
564
565 rule rl_write_data_splitting0(rg_wr_split_states == START_SPLIT && rg_awsize != 3);
566 rg_wr_ac_data <= rg_wr_ac_data | fn_wr_split_data(ff_wr_data.first.wdata,ff_wr_data.first.wstrb);
567 rg_wr_ac_wstrb <= rg_wr_ac_wstrb | ff_wr_data.first.wstrb;
568 rg_burst_counter <= rg_burst_counter + 1;
569 `ifdef verbose $display($time,"burst_eq: %h rg_packets: %h rg_packet_counter: %d rg_burst_counter: %d rg_local_actual_wr_length %d rg_wr_ac_data %h rg_wr_ac_wstrb %b",burst_eq,rg_packets,rg_packet_counter,rg_burst_counter,rg_local_actual_wr_length, fn_wr_split_data(ff_wr_data.first.wdata,ff_wr_data.first.wstrb), ff_wr_data.first.wstrb); `endif
570 if(burst_eq || rg_packets == rg_packet_counter) begin
571 rg_wr_split_states <= SEND_VALUE;
572 end
573 else begin
574 rg_packet_counter <= rg_packet_counter + 1;
575 end
576 ff_wr_data.deq();
577 ff_wr_addr.deq();
578 endrule
579
580 rule rl_write_data_splitting1(rg_wr_split_states == SEND_VALUE && rg_awsize != 3);
581 `ifdef verbose $display($stime,"Splitting1 Enqueued data rg_wr_ac_data %h rg_wr_ac_wstrb %b", rg_wr_ac_data, rg_wr_ac_wstrb); `endif
582 ff_ac_wr_data.enq(rg_wr_ac_data);
583 ff_ac_wr_wstrb.enq(rg_wr_ac_wstrb);
584 rg_wr_ac_data <= 0;
585 rg_wr_ac_wstrb <= 0;
586 rg_wr_lwr_addr <= 0;
587 rg_packet_counter <= 0;
588 `ifdef verbose $display($time,"Sending Value to the SDRAM"); `endif
589 rg_wr_split_states <= START_SPLIT;
590 endrule
591
592
593 rule rl_write_data_spliting3(rg_wr_split_states == START_SPLIT && rg_awsize == 3);
594 ff_ac_wr_data.enq(ff_wr_data.first.wdata);
595 ff_ac_wr_wstrb.enq(ff_wr_data.first.wstrb);
596 ff_wr_data.deq();
597 ff_wr_addr.deq();
598 endrule
599
600
601 rule rl_start_write_transaction(rg_write_states == IDLE && wr_sdr_init_done == True);
602 if(ff_ac_wr_data.notEmpty()) begin
603 if(rg_awsize_sclk == 0)
604 rg_write_states <= WAIT_DELAY;
605 else
606 rg_write_states <= WRITE_START;
607 `ifdef verbose $display($time,"\tSDRAM: Going to write start state"); `endif
608 end
609 endrule
610
611 rule rl_wait_delay(rg_write_states == WAIT_DELAY);
612 if(rg_delay_count == 14) begin
613 rg_write_states <= WRITE_START;
614 rg_delay_count <= 0;
615 end
616 else
617 rg_delay_count <= rg_delay_count + 1;
618 endrule
619
620 rule rl_write_transaction_write_start(rg_write_states == WRITE_START && wr_sdr_init_done == True && rg_read_states == IDLE);
621 `ifdef verbose $display($time,"\tSDRAM: WRITE_START state Controller Length %d",rg_actual_wr_length); `endif
622 rg_app_req <= 1;
623 rg_app_req_addr <= fn_wr_address(rg_wr_address);
624 rg_app_req_len <= extend(rg_actual_wr_length);
625 rg_app_req_wr_n <= 0;
626 rg_app_wr_data <= 0;
627 rg_app_wr_en_n <= 8'hFF;
628 rg_write_states <= WRITE_FIRST;
629 rg_delay_count <= extend(rg_actual_wr_length) - 1;
630 endrule
631
632 rule rl_write_transaction_write_first(rg_write_states == WRITE_FIRST && wr_app_wr_next_req == False);
633 `ifdef verbose $display($time,"\tSDRAM: WRITE_FIRST state next is false data %x",ff_ac_wr_data.first); `endif
634 rg_app_req <= 0;
635 rg_app_wr_en_n <= ~(ff_ac_wr_wstrb.first());
636 rg_app_wr_data <= ff_ac_wr_data.first();
637 endrule
638
639 rule rl_write_transaction_write_data(rg_write_states == WRITE_FIRST && wr_app_wr_next_req == True);
640 `ifdef verbose $display($time,"\tSDRAM: WRITE_DATA state next is true sending data %x %b",ff_ac_wr_data.first,wr_app_wr_next_req); `endif
641 rg_app_req <= 0;
642 rg_app_wr_data <= ff_ac_wr_data.first();
643 rg_app_wr_en_n <= ~(ff_ac_wr_wstrb.first());
644 ff_ac_wr_data.deq;
645 ff_ac_wr_wstrb.deq;
646 rg_delay_count <= rg_delay_count - 1;
647 if(rg_delay_count == 0) begin
648 rg_write_states <= IDLE;
649 ff_sync_write_response.enq(True);
650 end
651 endrule
652
653 rule synchronize_write_response(ff_sync_write_response.notEmpty);
654 ff_sync_write_response.deq;
655 let w_resp = AXI4_Wr_Resp {bresp: AXI4_OKAY, buser: 0, bid: rg_wid}; //TODO user value is null
656 s_xactor_sdram.i_wr_resp.enq(w_resp);
657 rg_wr_split_states <= IDLE;
658 rg_ac_count <= 0;
659 rg_wr_trnc_flg <= False;
660 `ifdef verbose $display($time,"\tSDRAM: WRITE complete state true"); `endif
661 endrule
662
663 /****************** Read Transaction ********************/
664 // `ifdef verbose
665 // rule display_read_states;
666 // $display($time,"\tSDRAM: Read State: ",fshow(rg_read_states));
667 // endrule
668 // `endif
669 rule rl_paralel_read_req_enq(rg_polling_status == True && rg_wr_trnc_flg == False);
670 let ar <- pop_o(s_xactor_sdram.o_rd_addr);
671 ff_rd_addr.enq(ar);
672 rg_rd_trnc_flg <= True;
673 `ifdef verbose $display($time,"\tSDRAM: Got Read request from AXI for AddresS: %h",ar.araddr); `endif
674 endrule
675
676 rule rl_read_idle_state(rg_read_states == IDLE);
677 if(ff_rd_addr.notEmpty() == True) begin
678 rg_read_states <= START_READ;
679 rg_rd_not_active_flag <= 0;
680 `ifdef verbose $display($time,"\tSDRAM: READ IDLE state"); `endif
681 end
682
683 endrule
684
685 rule rl_pop_read_request(wr_sdr_init_done == True && rg_read_states == START_READ && (rg_write_states == IDLE || rg_write_states == WRITE_START));
686 let ar = ff_rd_addr.first;
687 `ifdef verbose $display($time,"\tSDRAM: STAR_READ state ar.arlen %d ar.arsize %d ar.araddr %h ar.arburst %b", ar.arlen,ar.arsize, ar.araddr, ar.arburst); `endif
688
689 rg_app_req <= 1;
690 if(ar.arburst == 2)
691 rg_app_req_wrap <= 1;
692 else
693 rg_app_req_wrap <= 0;
694 rg_lwraddr <= extend(ar.araddr[2:0]);
695 rg_arsize <= ar.arsize;
696 rg_app_req_addr <= fn_wr_address(ar.araddr);
697 rg_app_req_len <= fn_wr_len(ar.arlen, ar.arsize, ar.araddr[2:0]);
698 rg_rd_actual_len <= extend(ar.arlen);
699 rg_app_req_wr_n <= 1;
700 rg_delay_count <= 0;
701 rg_read_states <= READ_DATA;
702 rg_rid <= ar.arid;
703 `ifdef verbose $display($time,"\t SSSSS SDRAM START_READ length "); `endif
704 endrule
705
706 rule rl_send_rd_data(wr_app_rd_valid == True);
707 `ifdef verbose $display($time,"\tSDRAM: READ DATA1 state %x",wr_app_rd_data); `endif
708 ff_rd_data.enq(wr_app_rd_data);
709 endrule
710
711 rule rl_send_read_data(rg_read_states==READ_DATA);
712 `ifdef verbose $display($time,"\tSDRAM: Response from BFM. RequestLenght: %d CurrentCount: %d",rg_rd_actual_len,rg_delay_count); `endif
713 rg_app_req_wrap <= 0;
714 if(rg_lwraddr < 8) begin
715 let r = AXI4_Rd_Data {rresp: AXI4_OKAY, rdata: fn_rd_data(rg_arsize, rg_lwraddr, ff_rd_data.first), rlast: (rg_rd_actual_len == rg_delay_count), ruser: 0, rid: rg_rid};
716 ff_sync_read_response.enq(r);
717 ff_rd_addr.deq;
718 if(rg_arsize!=3)
719 rg_lwraddr <= rg_lwraddr + (1 << rg_arsize);
720 else
721 ff_rd_data.deq;
722 `ifdef verbose $display($time,"\tSDRAM: SENDING READ DATA : %h, rg_lwraddr %b rg_arsize %d", fn_rd_data(rg_arsize, rg_lwraddr, ff_rd_data.first),rg_lwraddr, rg_arsize); `endif
723 `ifdef verbose $display($time,"\tSDRAM: Removing Request for Addr : %h",ff_rd_addr.first.araddr); `endif
724 if(rg_delay_count == rg_rd_actual_len) begin
725 `ifdef verbose $display($time,"\tSDRAM: SENT ALL READ DATA state rg_delay_count %d rg_rd_actual_len %d", rg_delay_count, rg_rd_actual_len); `endif
726 rg_read_states <= READ_FLUSH;
727 rg_rd_not_active_flag <= 1;
728 rg_delay_count <= 0;
729 end
730 else
731 rg_delay_count <= rg_delay_count + 1;
732 end
733 else if(rg_lwraddr > 7) begin
734 `ifdef verbose $display($time,"\tSDRAM: Dequeuing ff READ"); `endif
735 rg_lwraddr <= 0;
736 ff_rd_data.deq;
737 end
738 endrule
739
740 rule rl_flush_redundant_data(rg_read_states == READ_FLUSH);
741 ff_rd_data.clear();
742 rg_read_states <= IDLE;
743 endrule
744
745 rule send_synchronized_read_response(ff_sync_read_response.notEmpty);
746 let r=ff_sync_read_response.first;
747 `ifdef verbose $display($time,"\tSDRAM: Sending Read response: %h rlast: %b",r.rdata,r.rlast); `endif
748 ff_sync_read_response.deq;
749 if(rg_rd_not_active_flag == 1)
750 rg_rd_trnc_flg <= False;
751 s_xactor_sdram.i_rd_data.enq(r);
752 endrule
753
754
755
756
757
758 interface Ifc_sdram_out ifc_sdram_out;
759
760 interface ipad_sdr_din = interface Put
761 method Action put(Bit#(64) in);
762 sdr_cntrl.ipad_sdr_din(in);
763 endmethod
764 endinterface;
765
766 interface osdr_dout = interface Get
767 method ActionValue#(Bit#(64)) get;
768 return sdr_cntrl.osdr_dout();
769 endmethod
770 endinterface;
771
772 interface osdr_den_n = interface Get
773 method ActionValue#(Bit#(64)) get;
774 Bit#(64) temp = 0;
775 for (int i=0; i<8; i=i+1) begin
776 temp[i*8] = sdr_cntrl.osdr_den_n[i];
777 end
778 return temp;
779 endmethod
780 endinterface;
781
782 interface osdr_cke = interface Get
783 method ActionValue#(Bit#(1)) get;
784 return pack(sdr_cntrl.osdr_cke());
785 endmethod
786 endinterface;
787
788 interface osdr_cs_n = interface Get
789 method ActionValue#(Bit#(1)) get;
790 return pack(sdr_cntrl.osdr_cs_n());
791 endmethod
792 endinterface;
793
794 interface osdr_ras_n = interface Get
795 method ActionValue#(Bit#(1)) get;
796 return pack(sdr_cntrl.osdr_ras_n);
797 endmethod
798 endinterface;
799
800 interface osdr_cas_n = interface Get
801 method ActionValue#(Bit#(1)) get;
802 return pack(sdr_cntrl.osdr_cas_n);
803 endmethod
804 endinterface;
805
806 interface osdr_we_n = interface Get
807 method ActionValue#(Bit#(1)) get;
808 return pack(sdr_cntrl.osdr_we_n);
809 endmethod
810 endinterface;
811
812 interface osdr_dqm = interface Get
813 method ActionValue#(Bit#(8)) get;
814 return sdr_cntrl.osdr_dqm;
815 endmethod
816 endinterface;
817
818 interface osdr_ba = interface Get
819 method ActionValue#(Bit#(2)) get;
820 return sdr_cntrl.osdr_ba;
821 endmethod
822 endinterface;
823
824 interface osdr_addr = interface Get
825 method ActionValue#(Bit#(13)) get;
826 return sdr_cntrl.osdr_addr;
827 endmethod
828 endinterface;
829
830 interface osdr_clock = interface Get
831 method ActionValue#(Bit#(1)) get;
832 return rg_dummy;
833 endmethod
834 endinterface;
835 endinterface
836
837 interface axi4_slave_sdram = s_xactor_sdram.axi_side;
838 interface axi4_slave_cntrl_reg = s_xactor_cntrl_reg.axi_side;
839
840 endmodule
841 endpackage
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