src/peripherals/tdm/TCM.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
   6
   7 *  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
   8 *  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
   9 *  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
  10
  11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  13 */
  14 package TCM;
  15         /*====== Porject imports ====*/
  16         import defined_types::*;
  17         `include "defined_parameters.bsv"
  18         import Semi_FIFOF        :: *;
  19         import AXI4_Types   :: *;
  20         import AXI4_Fabric  :: *;
  21         import axi_addr_generator::*;
  22         /*==== Package imports ======*/
  23         import BRAMCore :: *;
  24         import DReg::*;
  25         import BUtils::*;
  26         /*============================*/
  27
  28         typedef TSub#(TLog#(TSub#(`TCMEnd,`TCMBase)),3) Index_bits;
  29
  30         interface Ifc_TCM;
  31                 interface AXI4_Slave_IFC#(`PADDR,`Reg_width,`USERSPACE) axi_slave;
  32         endinterface
  33         typedef enum{Idle,HandleBurst} Mem_state deriving(Bits,Eq, FShow);
  34         (*synthesize*)
  35         module mkTCM(Ifc_TCM);
  36
  37
  38                 let index_bits=valueOf(Index_bits);
  39                 BRAM_DUAL_PORT_BE#(Bit#(TSub#(TLog#(TSub#(`TCMEnd,`TCMBase)),3)), Bit#(32),4) dmemMSB <-mkBRAMCore2BE(valueOf(TExp#(Index_bits)),False);
  40                 BRAM_DUAL_PORT_BE#(Bit#(TSub#(TLog#(TSub#(`TCMEnd,`TCMBase)),3)), Bit#(32),4) dmemLSB <-mkBRAMCore2BE(valueOf(TExp#(Index_bits)),False);
  41
  42                 AXI4_Slave_Xactor_IFC #(`PADDR, `Reg_width, `USERSPACE)  s_xactor <- mkAXI4_Slave_Xactor;
  43
  44                 Reg#(Mem_state) rd_state <-mkReg(Idle);
  45                 Reg#(Mem_state) wr_state <-mkReg(Idle);
  46                 Reg#(Bit#(8)) rg_readburst_counter<-mkReg(0);
  47                 Reg#(AXI4_Rd_Addr       #(`PADDR,`USERSPACE)) rg_read_packet <-mkReg(?);                                                                                                                   // hold the read packet during bursts
  48                 Reg#(AXI4_Wr_Addr       #(`PADDR,`USERSPACE)) rg_write_packet<-mkReg(?); // hold the write packer during bursts
  49
  50                 rule rl_wr_respond(wr_state==Idle);
  51               let aw <- pop_o (s_xactor.o_wr_addr);
  52               let w  <- pop_o (s_xactor.o_wr_data);
  53                         Bit#(Index_bits) index_address=(aw.awaddr-`TCMBase)[index_bits+2:3];
  54                         dmemLSB.b.put(w.wstrb[3:0],index_address,truncate(w.wdata));
  55                         dmemMSB.b.put(w.wstrb[7:4],index_address,truncateLSB(w.wdata));
  56                    let b = AXI4_Wr_Resp {bresp: AXI4_OKAY, buser: aw.awuser, bid:aw.awid};
  57                         if(aw.awburst!=0) begin
  58                                 wr_state<=HandleBurst;
  59                                 let new_address=burst_address_generator(aw.awlen,aw.awsize,aw.awburst,aw.awaddr);
  60                                 aw.awaddr=new_address;
  61                                 rg_write_packet<=aw;
  62                         end
  63                         else
  64                         s_xactor.i_wr_resp.enq (b);
  65                         `ifdef verbose $display($time,"\t",module_name,":\t Recieved Write Request for Address: %h data: %h strb: %b awlen: %d",aw.awaddr,w.wdata,w.wstrb,aw.awlen);  `endif
  66                 endrule
  67
  68                 rule rl_wr_burst_response(wr_state==HandleBurst);
  69               let w  <- pop_o (s_xactor.o_wr_data);
  70                    let b = AXI4_Wr_Resp {bresp: AXI4_OKAY, buser: rg_write_packet.awuser, bid:rg_write_packet.awid};
  71                         if(w.wlast)begin
  72                                 wr_state<=Idle;
  73                                 s_xactor.i_wr_resp.enq (b);
  74                         end
  75                         Bit#(Index_bits) index_address=(rg_write_packet.awaddr-`TCMBase)[index_bits+2:3];
  76                         dmemLSB.b.put(w.wstrb[3:0],index_address,truncate(w.wdata));
  77                         dmemMSB.b.put(w.wstrb[7:4],index_address,truncateLSB(w.wdata));
  78                         let new_address=burst_address_generator(rg_write_packet.awlen,rg_write_packet.awsize,rg_write_packet.awburst,rg_write_packet.awaddr);
  79                         rg_write_packet.awaddr<=new_address;
  80                         `ifdef verbose $display($time,"\t",module_name,":\t BURST Write Request for Address: %h data: %h strb: %b awlen: %d",rg_write_packet.awaddr,w.wdata,w.wstrb,rg_write_packet.awlen);  `endif
  81                 endrule
  82
  83                 rule rl_rd_request(rd_state==Idle);
  84                         let ar<- pop_o(s_xactor.o_rd_addr);
  85                         rg_read_packet<=ar;
  86                         Bit#(Index_bits) index_address=(ar.araddr-`TCMBase)[index_bits+2:3];
  87                         dmemLSB.a.put(0,index_address,?);
  88                         dmemMSB.a.put(0,index_address,?);
  89                         rd_state<=HandleBurst;
  90                         `ifdef verbose $display($time,"\t",module_name,"\t Recieved Read Request for Address: %h Index Address: %h",ar.araddr,index_address);  `endif
  91                 endrule
  92
  93                 rule rl_rd_response(rd_state==HandleBurst);
  94                    Bit#(`Reg_width) data0 = {dmemMSB.a.read(),dmemLSB.a.read()};
  95               AXI4_Rd_Data#(`Reg_width,`USERSPACE) r = AXI4_Rd_Data {rresp: AXI4_OKAY, rdata: data0 ,rlast:rg_readburst_counter==rg_read_packet.arlen, ruser: 0, rid:rg_read_packet.arid};
  96                         let transfer_size=rg_read_packet.arsize;
  97                         let address=rg_read_packet.araddr;
  98                         if(transfer_size==2)begin // 32 bit
  99                                 if(address[2:0]==0)
 100                                         r.rdata=duplicate(data0[31:0]);
 101                                 else
 102                                         r.rdata=duplicate(data0[63:32]);
 103                         end
 104               else if (transfer_size=='d1)begin // half_word
 105                                 if(address[2:0] ==0)
 106                                         r.rdata = duplicate(data0[15:0]);
 107                                 else if(address[2:0] ==2)
 108                                         r.rdata = duplicate(data0[31:16]);
 109                                 else if(address[2:0] ==4)
 110                                         r.rdata = duplicate(data0[47:32]);
 111                                 else if(address[2:0] ==6)
 112                                         r.rdata = duplicate(data0[63:48]);
 113               end
 114               else if (transfer_size=='d0) begin// one byte
 115                                 if(address[2:0] ==0)
 116                           r.rdata = duplicate(data0[7:0]);
 117                         else if(address[2:0] ==1)
 118                           r.rdata = duplicate(data0[15:8]);
 119                         else if(address[2:0] ==2)
 120                           r.rdata = duplicate(data0[23:16]);
 121                         else if(address[2:0] ==3)
 122                           r.rdata = duplicate(data0[31:24]);
 123                         else if(address[2:0] ==4)
 124                                         r.rdata = duplicate(data0[39:32]);
 125                         else if(address[2:0] ==5)
 126                                         r.rdata = duplicate(data0[47:40]);
 127                         else if(address[2:0] ==6)
 128                                         r.rdata = duplicate(data0[55:48]);
 129                         else if(address[2:0] ==7)
 130                                         r.rdata = duplicate(data0[63:56]);
 131               end
 132               s_xactor.i_rd_data.enq(r);
 133                         address=burst_address_generator(rg_read_packet.arlen, rg_read_packet.arsize, rg_read_packet.arburst,rg_read_packet.araddr);
 134                         Bit#(Index_bits) index_address=(address-`TCMBase)[index_bits+2:3];
 135                         if(rg_readburst_counter==rg_read_packet.arlen)begin
 136                                 rg_readburst_counter<=0;
 137                                 rd_state<=Idle;
 138                         end
 139                         else begin
 140                                 dmemLSB.a.put(0,index_address,?);
 141                                 dmemMSB.a.put(0,index_address,?);
 142                                 rg_readburst_counter<=rg_readburst_counter+1;
 143                         end
 144                         rg_read_packet.araddr<=address;
 145                         Bit#(64) new_data=r.rdata;
 146                         `ifdef verbose $display($time,"\t",module_name,"\t Responding Read Request with CurrAddr: %h Data: %8h BurstCounter: %d BurstValue: %d NextAddress: %h",rg_read_packet.araddr,new_data,rg_readburst_counter,rg_read_packet.arlen,address);  `endif
 147            endrule
 148
 149            interface axi_slave= s_xactor.axi_side;
 150         endmodule
 151 endpackage