src/peripherals/vme/Memory_vme_8.bsv

   1
   2 /*
   3 Copyright (c) 2013, IIT Madras
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
   7
   8 *  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
   9 *  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  10 *  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
  11
  12 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  13 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  14 */
  15
  16 package Memory_vme_8;
  17         import defined_types::*;
  18        `include "instance_defines.bsv"
  19         import BRAMCore :: *;
  20
  21
  22 //typedef enum{Send_req,Get_resp} Mem_state deriving(Bits,Eq);
  23
  24 typedef enum
  25
  26 {RCV_REQ,DET_DS,END_REQ
  27 }State_slave deriving (Bits,Eq);
  28
  29 interface Vme_slave_8 #(numeric type base_address,numeric type mem_size);
  30 (*always_ready, always_enabled*)
  31 method Action rd_as_l(Bit#(1) m_as_l);
  32 (*always_ready, always_enabled*)
  33 method Action rd_ds_l(Bit#(1)m_ds_l);
  34 (*always_ready, always_enabled*)
  35 method Action rd_siz0(Bit#(1)m_ds1_l);
  36 (*always_ready, always_enabled*)
  37 method Action rd_siz1(Bit#(1)m_siz1);
  38 (*always_ready, always_enabled*)
  39 method Action rd_addr(Bit#(32)m_addr);
  40 (*always_ready, always_enabled*)
  41 method Action rd_wr_l(Bit#(1)m_wr_l);
  42 (*always_ready*)
  43 method Bit#(1) wr_dsack_0_l();
  44 (*always_ready*)
  45 method Bit#(1) wr_dsack_1_l();
  46 (*always_ready*)
  47 method Bit#(1) wr_berr_l();
  48 (*always_ready*)
  49 method Bit#(1) wr_halt_l();
  50
  51 //.........Methods to write and read data when tristate is not enabled.........//
  52
  53
  54 method Bit#(8) wr_byte_31_24();
  55 //method Bit#(8) wr_byte_23_16();
  56 //method Bit#(8) wr_byte_15_8();
  57 //method Bit#(8) wr_byte_7_0();
  58
  59 method Action rd_byte_31_24(Bit #(8) d3);
  60 //method Action rd_byte_23_16(Bit #(8) d2);
  61 //method Action rd_byte_15_8 (Bit #(8) d1);
  62 //method Action rd_byte_7_0  (Bit #(8) d0);
  63
  64
  65
  66 endinterface:Vme_slave_8
  67
  68 module mkMemory_8 #(parameter String mem_init_file, parameter String module_name) (Vme_slave_8#(base_address,mem_size));
  69
  70         BRAM_DUAL_PORT_BE#(Bit#(TSub#(mem_size,0)),Bit#(8),TDiv#(8,8)) dmemLSB <- mkBRAMCore2BELoad(valueOf(TExp#(TSub#(mem_size,0))),False,mem_init_file,False);
  71
  72 //Defining the slave interface lines
  73
  74 Reg #(Bit#(1)) s_dsack_0_l<-mkReg(1);
  75 Reg #(Bit#(1)) s_dsack_1_l<-mkReg(1);
  76 Reg #(Bit#(1)) s_berr_l<-mkReg(1);
  77 Reg #(Bit#(1)) s_halt_l<-mkReg(1);
  78 Wire #(Bit #(1)) s_as_l<-mkDWire(1);
  79 Wire #(Bit #(1)) s_ds_l<-mkDWire(1);
  80 Wire #(Bit #(1)) s_siz0<-mkDWire(0);
  81 Wire #(Bit #(1)) s_siz1<-mkDWire(0);
  82 Wire #(Bit #(32)) s_addr<-mkDWire(0);
  83 Wire #(Bit #(1)) s_wr_l<-mkDWire(0);
  84
  85
  86 Reg#(State_slave) slave_state <- mkReg (RCV_REQ);
  87
  88
  89 //..........data_out registers of tristate buffers and their control......
  90 //.......................................................................
  91
  92
  93 Wire#(Bit#(8)) data_in_4<-mkDWire(0);
  94 Wire#(Bit#(8)) data_in_3<-mkDWire(0);
  95 Wire#(Bit#(8)) data_in_2<-mkDWire(0);
  96 Wire#(Bit#(8)) data_in_1<-mkDWire(0);
  97
  98 Reg#(Bit#(8)) data_out_4<-mkReg(0);
  99 Reg#(Bit#(8)) data_out_3<-mkReg(0);
 100 Reg#(Bit#(8)) data_out_2<-mkReg(0);
 101 Reg#(Bit#(8)) data_out_1<-mkReg(0);
 102 Reg #(Bit#(4)) data_control <-mkReg(0);
 103
 104
 105
 106
 107
 108
 109
 110 /*In REQ_RCV State_slave
 111 1.If read, sends acknowledge on detecting data strobe low
 112   puts the data into the data bus
 113 2.If write,sends acknowledge on address strobe low
 114 */
 115
 116 Bool start_rd = (s_wr_l==1'b1)&&(s_ds_l==1'b0)&&(s_as_l==1'b0);
 117 Bool start_wr = (s_wr_l==1'b0)&&(s_as_l==1'b0);
 118 Bool store_data=(s_wr_l==1'b0)&&(s_ds_l==1'b0);
 119
 120 rule rcv_req((slave_state==RCV_REQ)&&(start_rd||start_wr));
 121
 122
 123         $display("............SELECTING SLAVE WITH PORT WIDTH 32...............");
 124         if(start_wr)
 125
 126
 127         begin
 128                 $display("Write_cycle");
 129                 s_dsack_0_l<=1'b0;
 130                 s_dsack_1_l<=1'b1;
 131                 slave_state<=DET_DS;
 132         end
 133         else
 134                 begin
 135                 $display("Starting read from address",$time);
 136
 137                 slave_state<=DET_DS;
 138                 Bit#(TSub#(mem_size,0)) index_address=(s_addr-fromInteger(valueOf(base_address)))[valueOf(mem_size)-1:0];
 139                 dmemLSB.b.put(0,index_address,?);
 140                 $display("Index Address : %h",index_address);
 141                 end
 142
 143 endrule
 144
 145 /*
 146 1. Checks for data_strobe
 147 2. Reads data if data_strobe is asserted
 148 */
 149
 150
 151 rule send_ack(slave_state==DET_DS );
 152         if(s_wr_l==1'b1)
 153         begin
 154                 s_dsack_0_l<=1'b0;
 155                 s_dsack_1_l<=1'b1;
 156                 slave_state<=END_REQ;
 157         Bit#(8) data0 = dmemLSB.b.read();
 158         $display("8 bit data_read : %h",data0,$time);
 159                                 case({s_siz1,s_siz0})
 160
 161                          2'b00:
 162                                begin
 163
 164                                                 data_out_4 <=data0;
 165                             //                  data_out_3 <=data0[23:16];
 166                             //                  data_out_2 <=data0[15:8];
 167                             //                  data_out_1 <=data0[7:0];
 168                                                 data_control<=4'b1111;
 169                                end
 170                         2'b01 :
 171                                case({s_addr[1],s_addr[0]})
 172                                         2'b00:begin
 173                                                 data_out_4<=data0;
 174                                                 data_control<=4'b1111;
 175                                                 //$display("Reading data %h from %h addr",data0[7:0],s_addr);
 176                                               end
 177                                         2'b01:begin
 178                                                 data_out_4<=data0;
 179                                                 data_control<=4'b1111;
 180                                                 //$display("Reading data %h from %h addr",data0[15:8],s_addr);
 181                                               end
 182                                         2'b10:begin
 183                                                 data_out_4<=data0;
 184                                                 data_control<=4'b1111;
 185                                         //      $display("Reading data %h from %h addr",data0[23:16],s_addr);
 186                                                 end
 187                                         2'b11:begin
 188                                                 data_out_4<=data0;
 189                                                 data_control<=4'b1111;
 190                                         //      $display("Reading data %h from %h addr",data0[31:24],s_addr);
 191                                                 end
 192
 193                                 endcase
 194                         2'b10 :
 195                                begin
 196                                         data_out_4<=data0;
 197                               //        data_out_3<=data0[7:0];
 198                                         data_control<=4'b1111;
 199                                end
 200                                /*else
 201                                begin
 202                                         data_out_2<=data0[31:24];
 203                                         data_out_1<=data0[23:16];
 204                                         data_control<=4'b1111;
 205                                end
 206                              */
 207                         endcase
 208
 209         end
 210           else  if(store_data)
 211
 212                 begin
 213                 $display("Writing to addr %0d ",s_addr,$time);
 214                 slave_state<=END_REQ;
 215                 Bit#(TSub#(mem_size,0)) index_address=(s_addr-fromInteger(valueOf(base_address)))[valueOf(mem_size)-1:0];
 216                 $display("Index_address : %h",index_address);
 217                 dmemLSB.b.put(1,index_address,data_in_4);
 218
 219                  end
 220
 221 endrule
 222
 223 //Releases bus if data strobe is released//
 224 rule end_req(slave_state==END_REQ);
 225
 226 if((s_ds_l==1) &&(s_as_l==1))
 227 begin
 228 s_dsack_0_l<=1;
 229 s_dsack_1_l<=1;
 230 s_berr_l<=1;
 231 s_halt_l<=1;
 232 data_control<=4'b0000;
 233 $display("SLAVE_STATE:3 Releasing bus ",$time);
 234 slave_state<=RCV_REQ;
 235 end
 236
 237 endrule
 238
 239
 240
 241 method Action rd_as_l(Bit#(1) m_as_l);
 242 s_as_l<=m_as_l;
 243 endmethod
 244
 245 method Action rd_ds_l(Bit#(1)m_ds_l);
 246 s_ds_l<=m_ds_l;
 247 endmethod
 248
 249 method Action rd_siz0(Bit#(1)m_ds1_l);
 250 s_siz0<=m_ds1_l;
 251 endmethod
 252
 253 method Action rd_siz1(Bit#(1)m_siz1);
 254 s_siz1<=m_siz1;
 255 endmethod
 256
 257 method Action rd_addr(Bit #(32)m_addr);
 258 s_addr<=m_addr;
 259
 260 endmethod
 261
 262 method Bit#(1) wr_dsack_0_l();
 263 return s_dsack_0_l;
 264 endmethod
 265
 266 method Bit#(1) wr_dsack_1_l();
 267 return s_dsack_1_l;
 268 endmethod
 269
 270 method Bit#(1)wr_berr_l();
 271 return s_berr_l;
 272 endmethod
 273
 274 method Bit#(1)wr_halt_l();
 275 return s_halt_l;
 276 endmethod
 277
 278
 279 method Action rd_wr_l(m_wr_l);
 280 s_wr_l<=m_wr_l;
 281 endmethod
 282
 283 /*Methods to emulate tristate functionality*/
 284
 285
 286 method Bit#(8) wr_byte_31_24()if(data_control[3]==1);
 287 return data_out_4;
 288 endmethod
 289
 290
 291 method Action rd_byte_31_24(Bit #(8) d4)if(data_control[3]==0);
 292 data_in_4<=d4;
 293 endmethod
 294
 295
 296 endmodule
 297 endpackage