import SpecialFIFOs:: *;
import Connectable :: *;
import ConfigReg :: *;
-`include "defined_parameters.bsv"
+`include "instance_defines.bsv"
// ----------------
// BSV additional libs
import Semi_FIFOF :: *;
import AXI4_Types :: *;
-import Memory_AXI4 :: *;
+//import Memory_AXI4 :: *;
// ****************************************************************
// ****************************************************************
// FlexBus External Signals
// AD inout bus separate for now in BSV
- (* result="AD" *) interface Get#(Bit#(32)) m_AD; // out
- interface Put#(Bit#(32) m_din; // in
-
- (* result="R_Wn" *) interface Get#(Bit#(1)) m_R_Wn; // out
- (* result="R_Wn" *) interface Get#(Bit#(1)) m_R_Wn; // out
- (* result="TSIZ" *) interface Get#(Bit #(2) m_TSIZ; // out
-
- (* result="FBCSn" *) interface Get#(Bit#(6)) m_FBCSn; // out
- (* result="BEn_BWEn" *) interface Get#(Bit#(4)) m_BE_BWEn; // out
- (* result="TBSTn" *) interface Get#(Bit#(1)) m_TBSTn; // out
- (* result="OEn" *) interface Get#(Bit#(1)) m_OEn; // out
-
- (* result="ALE" *) interface Get#(Bit#(1)) m_ALE; // out
- interface Put#(Bit#(1) tAn; // in
+ (* always_ready *)
+ interface Get#(Bit#(32)) m_AD; // out
+ (* always_ready *)
+ interface Put#(Bit#(32)) m_din; // in
+ (* always_ready *)
+ interface Get#(Bit#(32)) m_OE32n; // out 32-bits, same as OEn
+
+ (* always_ready *)
+ interface Get#(Bit#(1)) m_R_Wn; // out
+ (* always_ready *)
+ interface Get#(Bit#(2)) m_TSIZ; // out
+
+ (* always_ready *)
+ interface Get#(Bit#(6)) m_FBCSn; // out
+ (* always_ready *)
+ interface Get#(Bit#(4)) m_BWEn; // out
+ (* always_ready *)
+ interface Get#(Bit#(1)) m_TBSTn; // out
+ (* always_ready *)
+ interface Get#(Bit#(1)) m_OEn; // out
+
+ (* always_ready *)
+ interface Get#(Bit#(1)) m_ALE; // out
+ (* always_ready *)
+ interface Put#(Bit#(1)) m_tAn; // in
endinterface: FlexBus_Master_IFC
// These are the signal-level interfaces for an AXI4-Lite slave.
// The (*..*) attributes ensure that when bsc compiles this to Verilog,
// we get exactly the signals specified in the ARM spec.
-(* always_ready, always_enabled *)
interface FlexBus_Slave_IFC ;
+/*
(* result="AD" *) interface Put#(Bit#(32)) m_AD; // out
interface Get#(Bit#(32) m_din; // in
- (* result="R_Wn" *) interface Put#(Bit#(1)) m_R_Wn; // out
(* result="R_Wn" *) interface Put#(Bit#(1)) m_R_Wn; // out
(* result="TSIZ" *) interface Put#(Bit #(2) m_TSIZ; // out
(* result="ALE" *) interface Put#(Bit#(1)) m_ALE; // out
interface Get#(Bit#(1) tAn; // in
+*/
+
+ (* always_ready, always_enabled *)
+ method Action m_AD ( (* port="AD" *) Bit #(32) i_AD); // in
+
+
+ (* always_ready, always_enabled *)
+ method Action m_ALE ( (* port="ALE" *) Bit #(1) i_ALE); // in
+
+ (* always_ready, always_enabled *)
+ method Action m_R_Wn ( (* port="R_Wn" *) Bit #(1) i_R_Wn); // in
+ (* always_ready, always_enabled *)
+ method Action m_TSIZ ( (* port="TSIZ" *) Bit #(2) i_TSIZ); // in
+
+ (* always_ready, always_enabled *)
+ method Action m_FBCSn ( (* port="FBCSn" *) Bit #(6) i_FBCSn); // in
+ (* always_ready, always_enabled *)
+ method Action m_BE_BWEn( (* port="BE_BWEn" *) Bit #(4) i_BE_BWEn); // in
+ (* always_ready, always_enabled *)
+ method Action m_TBSTn ( (* port="TBSTn" *) Bit #(1) i_TBSTn); // in
+ (* always_ready, always_enabled *)
+ method Action m_OEn ( (* port="OEn" *) Bit #(1) i_OEn); // in
+
+ (* always_ready, result="din" *)
+ method Bit #(32) m_din; // out
+ (* always_ready, result="TAn" *)
+ method Bit #(1) m_TAn; // out
endinterface: FlexBus_Slave_IFC
// ================================================================
// Connecting signal-level interfaces
+`ifdef DISABLED_FOR_NOW // TODO. convert to get/put including slave ifc
instance Connectable #(FlexBus_Master_IFC ,
FlexBus_Slave_IFC );
endmodule
endinstance
+`endif
// ****************************************************************
// ****************************************************************
interface flexbus_side = interface FlexBus_Master_IFC;
//interface io_AD_master = tri_AD_out.io;
- interface c_TAn = interface Put
+ interface m_tAn = interface Put
method Action put(Bit#(1) in) if(c_TAn[0] matches tagged Invalid);
c_TAn[0] <= tagged Valid in;
endmethod
endmethod
endinterface;
- interface m_BE_BWEn = interface Get
+ interface m_BWEn = interface Get
method ActionValue#(Bit#(4)) get;
return r_BE_BWEn;
endmethod
endmethod
endinterface;
+ interface m_OE32n = interface Get
+ method ActionValue#(Bit#(32)) get;
+ Bit#(32) ten;
+ for (int i=0; i<32; i=i+1) begin
+ ten[i] = r_OEn;
+ end
+ return ten;
+ endmethod
+ endinterface;
+
interface m_OEn = interface Get
method ActionValue#(Bit#(1)) get;
return r_OEn;
endmodule: mkFlexBus_Registers
+`ifdef TESTING
+module mkVerfn_Top (Empty);
+
+/*
+ FlexBus_Slave_to_AXI4_Master_Fabric_IFC#(32,32,4)
+ verfn_ifc <- mkFlexBus_Slave_to_AXI4_Master_Fabric;
+ AXI4_Slave_to_FlexBus_Master_Xactor_IFC#(32, 32, 4)
+ flexbus_xactor_ifc <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
+
+ mkConnection(flexbus_xactor_ifc.flexbus_side,verfn_ifc.flexbus_side);
+*/
+
+ AXI4_Slave_to_FlexBus_Master_Xactor_IFC#(56, 64,10)
+ flexbus_xactor_ifc <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
+
+endmodule
+`endif
endpackage