add test and convert jtag to get/put
[shakti-peripherals.git] / src / peripherals / jtagdtm / Makefile
diff --git a/src/peripherals/jtagdtm/Makefile b/src/peripherals/jtagdtm/Makefile
new file mode 100644 (file)
index 0000000..4991d96
--- /dev/null
@@ -0,0 +1,45 @@
+### Makefile for the cclass project
+
+TOP_MODULE:=mkjtagdtm
+TOP_FILE:=jtagdtm.bsv
+TOP_DIR:=./
+WORKING_DIR := $(shell pwd)
+
+BSVINCDIR:= .:%/Prelude:%/Libraries:%/Libraries/BlueNoC:./bsv_lib/
+BSVINCDIR:= $(BSVINCDIR):../../uncore/axi4
+BSVINCDIR:= $(BSVINCDIR):../../lib
+BSVINCDIR:= $(BSVINCDIR):../../uncore/axi4lite
+BSVINCDIR:= $(BSVINCDIR):./test
+
+default: gen_verilog
+
+check-blue:
+       @if test -z "$$BLUESPECDIR"; then echo "BLUESPECDIR variable not set"; exit 1; fi; 
+
+###### Setting the variables for bluespec compile #$############################
+BSVCOMPILEOPTS:= -check-assert -suppress-warnings G0020 -keep-fires -opt-undetermined-vals -remove-false-rules -remove-empty-rules -remove-starved-rules 
+BSVLINKOPTS:=-parallel-sim-link 8 -keep-fires
+VERILOGDIR:=./verilog/
+BSVBUILDDIR:=./bsv_build/
+BSVOUTDIR:=./bin
+################################################################################
+
+########## BSIM COMPILE, LINK AND SIMULATE TARGETS ##########################
+.PHONY: check-restore
+check-restore:
+       @if [ "$(define_macros)" != "$(old_define_macros)" ];   then    make clean ;    fi;
+
+.PHONY: gen_verilog 
+gen_verilog: check-restore check-blue 
+       @echo Compiling mkTbSoc in Verilog for simulations ...
+       @mkdir -p $(BSVBUILDDIR); 
+       @mkdir -p $(VERILOGDIR); 
+       bsc -u -verilog -elab -vdir $(VERILOGDIR) -bdir $(BSVBUILDDIR) -info-dir $(BSVBUILDDIR) $(define_macros) -D verilog=True $(BSVCOMPILEOPTS) -verilog-filter ${BLUESPECDIR}/bin/basicinout -p $(BSVINCDIR) -g $(TOP_MODULE) $(TOP_DIR)/$(TOP_FILE) 2>&1 | tee bsv_compile.log
+       @echo Compilation finished
+
+#############################################################################
+
+.PHONY: clean
+clean:
+       rm -rf $(BSVBUILDDIR) *.log $(BSVOUTDIR) ./bbl*
+       rm -rf verilog obj_dir bsv_src