add rgbttl interface

diff --git a/src/peripherals/rgbttl/rgbttl_dummy.bsv b/src/peripherals/rgbttl/rgbttl_dummy.bsv
new file mode 100644 (file)
index 0000000..3bdb054
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+++ b/src/peripherals/rgbttl/rgbttl_dummy.bsv
@@ -0,0 +1,70 @@
+/* 
+Copyright (c) 2013, IIT Madras All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification, are permitted
+provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this list of conditions
+  and the following disclaimer.  
+* Redistributions in binary form must reproduce the above copyright notice, this list of 
+  conditions and the following disclaimer in the documentation and/or other materials provided 
+ with the distribution.  
+* Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or 
+  promote products derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS
+OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 
+OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--------------------------------------------------------------------------------------------------
+
+Author: Neel Gala
+Email id: neelgala@gmail.com
+Details:
+
+--------------------------------------------------------------------------------------------------
+*/
+package rgbttl_dummy;
+  `include "instance_defines.bsv"
+  import ClockDiv::*;
+  import ConcatReg::*;
+  import Semi_FIFOF::*;
+  import BUtils ::*;
+  import AXI4_Lite_Types::*;
+
+  interface Ifc_rgbttl_dummy#(numeric type buswidth);
+         interface AXI4_Lite_Slave_IFC#(`ADDR, `DATA, `USERSPACE) slave;
+    method  Bit#(1) de; 
+    method  Bit#(1) ck;
+    method  Bit#(1) vs;
+    method  Bit#(1) hs;
+    method  Bit#(buswidth) data;
+  endinterface
+
+  (*synthesize*)
+  module mkrgbttl_dummy(Ifc_rgbttl_dummy#(numeric type buswidth));
+               AXI4_Lite_Slave_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
+                            s_xactor<-mkAXI4_Lite_Slave_Xactor();
+      let v_buswidth = valueOf(v_buswidth);
+
+      Reg#(Bit#(1)) rg_de <- mkReg(0);
+      Reg#(Bit#(1)) rg_ck <- mkReg(0);
+      Reg#(Bit#(1)) rg_vs <- mkReg(0);
+      Reg#(Bit#(1)) rg_hs <- mkReg(0);
+      Reg#(Bit#(v_buswidth)) rg_data;
+      for(Integer i = 0; i < v_no_of_ir_pins;i=i+1) begin
+        rg_data[i] <- mkReg(0);
+      end
+
+    method  de = rg_de; 
+    method  ck = rg_ck;
+    method  vs = rg_vs;
+    method  hs = rg_hs;
+    method  data = rg_data;
+    interface slave=s_xactor.axi_side;
+  endmodule
+endpackage