move clk and cfg
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 1 Aug 2018 12:38:41 +0000 (13:38 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 1 Aug 2018 12:38:41 +0000 (13:38 +0100)
src/peripherals/sdram/sdr_top.bsv

index 373fc9f..181f6de 100644 (file)
@@ -62,14 +62,14 @@ interface Ifc_sdram_out;
     interface Get#(Bit#(2))  osdr_ba;
     interface Get#(Bit#(13)) osdr_addr;
 
-    method Bit#(9) sdram_sdio_ctrl;
-    interface Clock sdram_clk;    
 endinterface
 
 interface Ifc_sdr_slave;
       interface AXI4_Slave_IFC#(`PADDR, `Reg_width,`USERSPACE) axi4_slave_sdram;
       interface AXI4_Slave_IFC#(`PADDR, `Reg_width,`USERSPACE) axi4_slave_cntrl_reg;
       interface Ifc_sdram_out ifc_sdram_out;
+      method Bit#(9) sdram_sdio_ctrl;
+      interface Clock sdram_clk;    
 endinterface
 
 typedef enum{
@@ -830,12 +830,12 @@ module mksdr_axi4_slave#(Clock clk0) (Ifc_sdr_slave);
           endmethod
         endinterface;
 
-        interface sdram_clk = clk0;
-        method Bit#(9) sdram_sdio_ctrl();
-            return rg_cfg_sdio_ctrl;
-        endmethod
     endinterface
 
+    interface sdram_clk = clk0;
+    method Bit#(9) sdram_sdio_ctrl();
+        return rg_cfg_sdio_ctrl;
+    endmethod
 
     interface axi4_slave_sdram = s_xactor_sdram.axi_side;
     interface axi4_slave_cntrl_reg = s_xactor_cntrl_reg.axi_side;