providing default values of the mux to be compile time defined

diff --git a/src/peripherals/mux/mux.bsv b/src/peripherals/mux/mux.bsv
index d7ff5f684924dd844a00e6c23c790ffe00618458..39c48fa0fec85d6321f2949807e85cb6de67ac7d 100644 (file)
--- a/src/peripherals/mux/mux.bsv
+++ b/src/peripherals/mux/mux.bsv
@@ -35,11 +35,13 @@ package mux;
        endinterface
 
 //     (*synthesize*)
-       module mkmux(MUX#(ionum_));
-         Vector#(ionum_,ConfigReg#(Bit#(2))) muxer_reg                                 <-replicateM(mkConfigReg(0));
+       module mkmux#(Bit#(TMul#(ionum_, 2)) defvalue)(MUX#(ionum_));
+    let ionum=valueOf(ionum_);
+         Vector#(ionum_,ConfigReg#(Bit#(2))) muxer_reg                                 
+    for(Integer i=0;i<ionum;i=i+ 1)
+      muxer_reg[i]<-mkConfigReg(defvalue[i*2+ 1:i*2]);
                
                AXI4_Lite_Slave_Xactor_IFC #(`PADDR, `DATA, `USERSPACE)  s_xactor <- mkAXI4_Lite_Slave_Xactor;
-    let ionum=valueOf(ionum_);
                rule rl_wr_respond;
                        // Get the wr request
             //aw is write address, w is write data