Merge branch 'master' of libre-riscv.org:shakti-peripherals

diff --git a/src/lib/ifc_sync.bsv b/src/lib/ifc_sync.bsv
new file mode 100644 (file)
index 0000000..49da823
--- /dev/null
+++ b/src/lib/ifc_sync.bsv
@@ -0,0 +1,35 @@
+package ifc_sync;
+
+  import Clocks::*;
+  import GetPut::*;
+
+  (*always_ready,always_enabled*)
+  interface Ifc_sync#(type a);
+    (*always_ready,always_enabled*)
+    interface Put#(a) put;
+    (*always_ready,always_enabled*)
+    interface Get#(a) get;
+  endinterface
+  module mksyncconnection#(Clock putclock, Reset putreset,
+                           Clock getclock, Reset getreset)(Ifc_sync#(a))
+    provisos(Bits#(a, a__));
+    CrossingReg#(a) null_wire<- mkNullCrossingReg(getclock,?,
+                                        clocked_by putclock,
+                                        reset_by putreset);
+ //   ReadOnly#(Bit#(a)) null_wire <- mkNullCrossingWire(getclock, 
+//                                  from_put, clocked_by getclock,
+//                                  reset_by getreset);
+    interface put = interface Put
+      method Action put(a in);
+        null_wire<= in;
+      endmethod
+    endinterface;
+    interface get = interface Get
+      method ActionValue#(a) get();
+        return null_wire.crossed;
+      endmethod
+    endinterface;
+  endmodule
+
+endpackage
+

diff --git a/src/peripherals/bootrom/BootRom.bsv b/src/peripherals/bootrom/BootRom.bsv
index cd67f37ceabf4b41de2b9eb6f034f4b428ee72bc..04f185b36fd5c67b4e8930ce094eeb95c02897f1 100644 (file)
--- a/src/peripherals/bootrom/BootRom.bsv
+++ b/src/peripherals/bootrom/BootRom.bsv
@@ -13,7 +13,7 @@ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 */
 package BootRom;
        import defined_types::*;
-       `include "defined_parameters.bsv"
+       `include "instance_defines.bsv"
        import BRAMCore :: *;
        import DReg::*;
        import Semi_FIFOF        :: *;

diff --git a/src/peripherals/clint/clint.bsv b/src/peripherals/clint/clint.bsv
index cdd4f4f3bcb288e67a1de9dff5801b539583fbae..270ec0f2a61e6f08c12824f20a7f3b8d3186972b 100644 (file)
--- a/src/peripherals/clint/clint.bsv
+++ b/src/peripherals/clint/clint.bsv
@@ -21,7 +21,7 @@ package clint;
        /*======================== */
        /*==== Project imports ====*/
        import defined_types::*;
-       `include "defined_parameters.bsv"       
+       `include "instance_defines.bsv" 
        /*=========================*/
 
        interface Ifc_clint;

diff --git a/src/peripherals/dma/DMA.bsv b/src/peripherals/dma/DMA.bsv
index ac511204598e81a923d9c18d163fe78d384abcd1..3d1cced67087ab621860a9bf2e1bc2fb166f0b09 100644 (file)
--- a/src/peripherals/dma/DMA.bsv
+++ b/src/peripherals/dma/DMA.bsv
@@ -38,7 +38,7 @@ import ConcatReg :: *;
 import ConfigReg :: *;
 
 `define Burst_length_bits 8
-`include "defined_parameters.bsv"
+`include "instance_defines.bsv"
 `define verbose
 // ================================================================
 // DMA requests and responses parameters

diff --git a/src/peripherals/dma/tb_DMA.bsv b/src/peripherals/dma/tb_DMA.bsv
index d0a085f04194cb8cdbc97ee8205b9ea912437d8d..1dc72450c12424ace854de627336c3190f7e397b 100644 (file)
--- a/src/peripherals/dma/tb_DMA.bsv
+++ b/src/peripherals/dma/tb_DMA.bsv
@@ -23,7 +23,7 @@ package tb_DMA;
        import Clocks :: * ;
        import DReg ::*;
        import defined_types::*;
-       `include "defined_parameters.bsv"
+       `include "instance_defines.bsv"
 
 
        `define Num_DMA_Channels 7

diff --git a/src/peripherals/dma/tb_DMA_AXI_Memory.bsv b/src/peripherals/dma/tb_DMA_AXI_Memory.bsv
index 7c070efec654c91324862033b1865da9f862cd26..7701a6c9c8804f1f6b753fcbff15fc5c99f82d6e 100644 (file)
--- a/src/peripherals/dma/tb_DMA_AXI_Memory.bsv
+++ b/src/peripherals/dma/tb_DMA_AXI_Memory.bsv
@@ -23,7 +23,7 @@ package tb_DMA_AXI_Memory;
        import RegFile::*;
        import Clocks :: * ;
        import DReg ::*;
-       `include "defined_parameters.bsv"
+       `include "instance_defines.bsv"
        typedef 2 Num_Masters;
        typedef 3 Num_Slaves;
 

diff --git a/src/peripherals/flexbus/FlexBus_Types.bsv b/src/peripherals/flexbus/FlexBus_Types.bsv
index f46fae5d90888936d2adad6cac0d356940cc2cc6..19ba1a49057d3c46b101d9c792a466b0f5e57971 100644 (file)
--- a/src/peripherals/flexbus/FlexBus_Types.bsv
+++ b/src/peripherals/flexbus/FlexBus_Types.bsv
@@ -67,19 +67,30 @@ interface FlexBus_Master_IFC;
    // FlexBus External Signals
   
    // AD inout bus separate for now in BSV
+   (* always_ready *)
    interface Get#(Bit#(32)) m_AD;      // out
+   (* always_ready *)
    interface Put#(Bit#(32)) m_din;     // in
+   (* always_ready *)
    interface Get#(Bit#(32)) m_OE32n;   // out 32-bits, same as OEn
 
+   (* always_ready *)
    interface Get#(Bit#(1))  m_R_Wn;    // out
+   (* always_ready *)
    interface Get#(Bit#(2))  m_TSIZ;    // out
 
+   (* always_ready *)
    interface Get#(Bit#(6))  m_FBCSn;   // out
+   (* always_ready *)
    interface Get#(Bit#(4))  m_BWEn; // out
+   (* always_ready *)
    interface Get#(Bit#(1))  m_TBSTn;   // out
+   (* always_ready *)
    interface Get#(Bit#(1))  m_OEn;     // out
 
+   (* always_ready *)
    interface Get#(Bit#(1))  m_ALE;     // out
+   (* always_ready *)
    interface Put#(Bit#(1))  m_tAn;     // in
 
 endinterface: FlexBus_Master_IFC

diff --git a/src/peripherals/gpio/gpio.bsv b/src/peripherals/gpio/gpio.bsv
index 64f76fcdc917bc2ee179e3cd2218c089899f70f8..df55b67eea41f6a8a6a6449b514e798453f12d7b 100644 (file)
--- a/src/peripherals/gpio/gpio.bsv
+++ b/src/peripherals/gpio/gpio.bsv
@@ -56,7 +56,7 @@ package gpio;
   interface GPIO#(numeric type ionum);
     interface GPIO_config#(ionum) pad_config;
     interface GPIO_func#(ionum) func;
-               interface AXI4_Lite_Slave_IFC#(`ADDR,`DATA,`USERSPACE) axi_slave;
+               interface AXI4_Lite_Slave_IFC#(`PADDR,`DATA,`USERSPACE) axi_slave;
        endinterface
 
        module mkgpio(GPIO#(ionum_));
@@ -74,7 +74,7 @@ package gpio;
                Vector#(ionum_,ConfigReg#(Bit#(1))) pwrupzhl_reg        <-replicateM(mkConfigReg(0));   
                Vector#(ionum_,ConfigReg#(Bit#(1))) pwrup_pull_en_reg   <-replicateM(mkConfigReg(0));   
                
-               AXI4_Lite_Slave_Xactor_IFC #(`ADDR, `DATA, `USERSPACE)  s_xactor <- mkAXI4_Lite_Slave_Xactor;
+               AXI4_Lite_Slave_Xactor_IFC #(`PADDR, `DATA, `USERSPACE)  s_xactor <- mkAXI4_Lite_Slave_Xactor;
                rule rl_wr_respond;
                        // Get the wr request
        let aw <- pop_o (s_xactor.o_wr_addr);

diff --git a/src/peripherals/jtagdtm/Makefile b/src/peripherals/jtagdtm/Makefile
new file mode 100644 (file)
index 0000000..4991d96
--- /dev/null
+++ b/src/peripherals/jtagdtm/Makefile
@@ -0,0 +1,45 @@
+### Makefile for the cclass project
+
+TOP_MODULE:=mkjtagdtm
+TOP_FILE:=jtagdtm.bsv
+TOP_DIR:=./
+WORKING_DIR := $(shell pwd)
+
+BSVINCDIR:= .:%/Prelude:%/Libraries:%/Libraries/BlueNoC:./bsv_lib/
+BSVINCDIR:= $(BSVINCDIR):../../uncore/axi4
+BSVINCDIR:= $(BSVINCDIR):../../lib
+BSVINCDIR:= $(BSVINCDIR):../../uncore/axi4lite
+BSVINCDIR:= $(BSVINCDIR):./test
+
+default: gen_verilog
+
+check-blue:
+       @if test -z "$$BLUESPECDIR"; then echo "BLUESPECDIR variable not set"; exit 1; fi; 
+
+###### Setting the variables for bluespec compile #$############################
+BSVCOMPILEOPTS:= -check-assert -suppress-warnings G0020 -keep-fires -opt-undetermined-vals -remove-false-rules -remove-empty-rules -remove-starved-rules 
+BSVLINKOPTS:=-parallel-sim-link 8 -keep-fires
+VERILOGDIR:=./verilog/
+BSVBUILDDIR:=./bsv_build/
+BSVOUTDIR:=./bin
+################################################################################
+
+########## BSIM COMPILE, LINK AND SIMULATE TARGETS ##########################
+.PHONY: check-restore
+check-restore:
+       @if [ "$(define_macros)" != "$(old_define_macros)" ];   then    make clean ;    fi;
+
+.PHONY: gen_verilog 
+gen_verilog: check-restore check-blue 
+       @echo Compiling mkTbSoc in Verilog for simulations ...
+       @mkdir -p $(BSVBUILDDIR); 
+       @mkdir -p $(VERILOGDIR); 
+       bsc -u -verilog -elab -vdir $(VERILOGDIR) -bdir $(BSVBUILDDIR) -info-dir $(BSVBUILDDIR) $(define_macros) -D verilog=True $(BSVCOMPILEOPTS) -verilog-filter ${BLUESPECDIR}/bin/basicinout -p $(BSVINCDIR) -g $(TOP_MODULE) $(TOP_DIR)/$(TOP_FILE) 2>&1 | tee bsv_compile.log
+       @echo Compilation finished
+
+#############################################################################
+
+.PHONY: clean
+clean:
+       rm -rf $(BSVBUILDDIR) *.log $(BSVOUTDIR) ./bbl*
+       rm -rf verilog obj_dir bsv_src

diff --git a/src/peripherals/jtagdtm/jtagdtm.bsv b/src/peripherals/jtagdtm/jtagdtm.bsv
index aea5b3701f2bcf0bfe62db57560ca67f6348630a..3bb63a369e42a7111d643969ee494ad910cf2cca 100644 (file)
--- a/src/peripherals/jtagdtm/jtagdtm.bsv
+++ b/src/peripherals/jtagdtm/jtagdtm.bsv
@@ -15,13 +15,14 @@ package jtagdtm;
 /*====== Package imports ======= */
        import Clocks::*;
        import ConcatReg::*;
+       import GetPut::*;
        import FIFO::*;
        import FIFOF::*;
        import SpecialFIFOs::*;
        import DReg::*;
 /*======= Project imports ===== */
        `include "jtagdefines.bsv"
-       import defined_types::*;
+       //import defined_types::*;
 /*============================== */
 
 interface Ifc_jtagdtm;
@@ -69,15 +70,17 @@ interface Ifc_jtagdtm;
        method Bit#(1) scan_shift_en;
        /*======== JTAG input pins ===== */
        (*always_enabled,always_ready*)
-       method Action tms_i(Bit#(1) tms);
+    interface Put#(Bit#(1)) tms;
        (*always_enabled,always_ready*)
-       method Action tdi_i(Bit#(1) tdi);
+    interface Put#(Bit#(1)) tdi;
        /*==== inputs from Sub-modules === */
        method Action debug_tdi_i(Bit#(1) debug_tdi);
        /*======= JTAG Output Pins ====== */
        (*always_enabled,always_ready*)
-       method Bit#(1) tdo;
-       method Bit#(1) tdo_oe;
+    interface Get#(Bit#(1)) tdo;
+       (*always_enabled,always_ready*)
+    interface Get#(Bit#(1)) tck;
+
        /*======== TAP States ============= */
        method Bit#(1) shift_dr;
        method Bit#(1) pause_dr;
@@ -514,12 +517,19 @@ typedef enum {TestLogicReset = 4'h0,  RunTestIdle    = 4'h1,  SelectDRScan   = 4
                scan_out_5_sr<=scan_out_5;
        endmethod
        /*======== JTAG input pins ===== */
-       method Action tms_i(Bit#(1) tms);
-               wr_tms<=tms;
-       endmethod
-       method Action tdi_i(Bit#(1) tdi);
-               wr_tdi<=tdi;
-       endmethod
+
+    interface tms = interface Put
+        method Action put(Bit#(1) in);
+                 wr_tms<=in;
+        endmethod
+    endinterface;
+
+    interface tdi = interface Put
+        method Action put(Bit#(1) in);
+          wr_tdi<=in;
+        endmethod
+    endinterface;
+
        /*============================= */
        method Action debug_tdi_i(Bit#(1) debug_tdi);
                wr_debug_tdi<=debug_tdi;
@@ -552,9 +562,19 @@ typedef enum {TestLogicReset = 4'h0,  RunTestIdle    = 4'h1,  SelectDRScan   = 4
        method bscan_in   = bs_sr;
        method scan_shift_en = wr_scan_shift_en[1];
        /*======= JTAG Output Pins ====== */
-       method tdo = crossed_output_tdo;
+    interface tck = interface Get
+        method ActionValue#(Bit#(1)) get;
+          return ((tapstate == ShiftIR) || (tapstate == ShiftDR))?1:0;
+        endmethod
+    endinterface;
+
+    interface tdo = interface Get
+        method ActionValue#(Bit#(1)) get;
+          return crossed_output_tdo;
+        endmethod
+    endinterface;
+
        method debug_tdo = wr_tdi;
-       method Bit#(1) tdo_oe = ((tapstate == ShiftIR) || (tapstate == ShiftDR))?1:0;
        method Action response_from_dm(Bit#(34) responsedm) if(response_from_DM.notFull);
                if(capture_repsonse_from_dm)
                        response_from_DM.enq(responsedm);

diff --git a/src/peripherals/jtagdtm/test/instance_defines.bsv b/src/peripherals/jtagdtm/test/instance_defines.bsv
new file mode 100644 (file)
index 0000000..38780f5
--- /dev/null
+++ b/src/peripherals/jtagdtm/test/instance_defines.bsv
@@ -0,0 +1,24 @@
+`define ADDR 32
+`define PADDR 32
+`define DATA 64
+`define Reg_width 64
+`define USERSPACE 0
+
+// TODO: work out if these are needed
+`define PWM_AXI4Lite
+`define PRFDEPTH 6
+`define VADDR 39
+`define DCACHE_BLOCK_SIZE 4
+`define DCACHE_WORD_SIZE 8
+`define PERFMONITORS                            64
+`define DCACHE_WAYS 4
+`define DCACHE_TAG_BITS 20      // tag_bits = 52
+`define PLIC
+       `define PLICBase                'h0c000000
+       `define PLICEnd         'h10000000
+`define INTERRUPT_PINS 64
+
+`define BAUD_RATE 130
+`ifdef simulate
+  `define BAUD_RATE 5 //130 //
+`endif

diff --git a/src/peripherals/mux/mux.bsv b/src/peripherals/mux/mux.bsv
index cb6745867399402ed43e97ef55c9c80fe873dc9a..d7ff5f684924dd844a00e6c23c790ffe00618458 100644 (file)
--- a/src/peripherals/mux/mux.bsv
+++ b/src/peripherals/mux/mux.bsv
@@ -31,14 +31,14 @@ package mux;
 
        interface MUX#(numeric type ionum);
         interface MUX_config#(ionum) mux_config;
-            interface AXI4_Lite_Slave_IFC#(`ADDR,`DATA,`USERSPACE) axi_slave;
+            interface AXI4_Lite_Slave_IFC#(`PADDR,`DATA,`USERSPACE) axi_slave;
        endinterface
 
 //     (*synthesize*)
        module mkmux(MUX#(ionum_));
          Vector#(ionum_,ConfigReg#(Bit#(2))) muxer_reg                                 <-replicateM(mkConfigReg(0));
                
-               AXI4_Lite_Slave_Xactor_IFC #(`ADDR, `DATA, `USERSPACE)  s_xactor <- mkAXI4_Lite_Slave_Xactor;
+               AXI4_Lite_Slave_Xactor_IFC #(`PADDR, `DATA, `USERSPACE)  s_xactor <- mkAXI4_Lite_Slave_Xactor;
     let ionum=valueOf(ionum_);
                rule rl_wr_respond;
                        // Get the wr request

diff --git a/src/peripherals/rgbttl/rgbttl_dummy.bsv b/src/peripherals/rgbttl/rgbttl_dummy.bsv
index a52d5e7db27f36ee367a652d6a0ea0c6dbe3284f..35598d324729affd34701527c59ba2944c748585 100644 (file)
--- a/src/peripherals/rgbttl/rgbttl_dummy.bsv
+++ b/src/peripherals/rgbttl/rgbttl_dummy.bsv
@@ -36,20 +36,20 @@ package rgbttl_dummy;
   import AXI4_Types::*;
 
   interface Ifc_rgbttl_dummy;
-           interface AXI4_Master_IFC#(`ADDR, `DATA, `USERSPACE) master;
-           interface AXI4_Slave_IFC#(`ADDR, `DATA, `USERSPACE) slave;
-      interface Get#(Bit#(1)) de;
-      interface Get#(Bit#(1)) ck;
-      interface Get#(Bit#(1)) vs;
-      interface Get#(Bit#(1)) hs;
-      interface Get#(Bit#(`RGBTTL_WIDTH)) data_out;
+           interface AXI4_Master_IFC#(`PADDR, `DATA, `USERSPACE) master;
+           interface AXI4_Slave_IFC#(`PADDR, `DATA, `USERSPACE) slave;
+      (* always_ready *) interface Get#(Bit#(1)) de;
+      (* always_ready *) interface Get#(Bit#(1)) ck;
+      (* always_ready *) interface Get#(Bit#(1)) vs;
+      (* always_ready *) interface Get#(Bit#(1)) hs;
+      (* always_ready *) interface Get#(Bit#(`RGBTTL_WIDTH)) data_out;
   endinterface
 
   (*synthesize*)
   module mkrgbttl_dummy(Ifc_rgbttl_dummy);
-               AXI4_Slave_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
+               AXI4_Slave_Xactor_IFC#(`PADDR,`DATA, `USERSPACE)
                             s_xactor<-mkAXI4_Slave_Xactor();
-               AXI4_Master_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
+               AXI4_Master_Xactor_IFC#(`PADDR,`DATA, `USERSPACE)
                             m_xactor<-mkAXI4_Master_Xactor();
 
       Reg#(Bit#(1)) rg_de <- mkReg(0);

diff --git a/src/peripherals/sdmmc/sdcard_dummy.bsv b/src/peripherals/sdmmc/sdcard_dummy.bsv
index 823394b2dc8880e2bcc4c90cf5de66995e1744b1..9e44c67625ced11a9fb782cabd02f1b9ae0445cf 100644 (file)
--- a/src/peripherals/sdmmc/sdcard_dummy.bsv
+++ b/src/peripherals/sdmmc/sdcard_dummy.bsv
@@ -45,7 +45,7 @@ package sdcard_dummy;
        import AXI4_Lite_Types::*;
 
   interface Ifc_sdcard_dummy;
-         interface AXI4_Lite_Slave_IFC#(`ADDR, `DATA, `USERSPACE) slave;
+         interface AXI4_Lite_Slave_IFC#(`PADDR, `DATA, `USERSPACE) slave;
     interface Get#(Bit#(1)) cmd;
     interface Get#(Bit#(1)) clk;
     interface Get#(Bit#(`SDBUSWIDTH)) out;
@@ -55,7 +55,7 @@ package sdcard_dummy;
 
   (*synthesize*)
   module mksdcard_dummy(Ifc_sdcard_dummy);
-               AXI4_Lite_Slave_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
+               AXI4_Lite_Slave_Xactor_IFC#(`PADDR,`DATA, `USERSPACE)
                 s_xactor<-mkAXI4_Lite_Slave_Xactor();
 
       Reg#(Bit#(1)) rg_cmd <- mkReg(0);

diff --git a/src/peripherals/sdram/sdr_top.bsv b/src/peripherals/sdram/sdr_top.bsv
index a33e06d53309a58db9780e9b6378fd4692a4fe88..ec1d82167c6112fb7b77f9e8dd93d17cfcbb5e85 100644 (file)
--- a/src/peripherals/sdram/sdr_top.bsv
+++ b/src/peripherals/sdram/sdr_top.bsv
@@ -12,7 +12,7 @@ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 */
 
-`include "defined_parameters.bsv"
+`include "instance_defines.bsv"
 `define DELAY 250
 `define SDR_RFSH_TIMER_W    12
 `define SDR_RFSH_ROW_CNT_W  3

diff --git a/src/peripherals/sdram/tb_bsv_wrapper.bsv b/src/peripherals/sdram/tb_bsv_wrapper.bsv
index a834b29ce260597615dce2412fa7e52351856d8d..38f1042fdb8bad9779f8039f8f7dfab19bbef550 100644 (file)
--- a/src/peripherals/sdram/tb_bsv_wrapper.bsv
+++ b/src/peripherals/sdram/tb_bsv_wrapper.bsv
@@ -18,7 +18,7 @@ import AXI4_Types   :: *;
 import AXI4_Fabric  :: *;
 import bsvmksdram_model_wrapper :: *;
 import Connectable       :: *;
-`include "defined_parameters.bsv"
+`include "instance_defines.bsv"
 
 `define DELAY 10200
 

diff --git a/src/peripherals/sdram/tb_top.bsv b/src/peripherals/sdram/tb_top.bsv
index 8e920a08b1db4770631c3300da5a88a68515fbcb..4cba9212b134bf0db007f97a88decf1afa7f4508 100644 (file)
--- a/src/peripherals/sdram/tb_top.bsv
+++ b/src/peripherals/sdram/tb_top.bsv
@@ -19,7 +19,7 @@ import AXI4_Fabric  :: *;
 import sdr_top           :: *;
 import tb_bsv_wrapper    :: *;
 import Connectable       :: *;
-`include "defined_parameters.bsv"
+`include "instance_defines.bsv"
 
 
 typedef 1 Num_Masters;

diff --git a/src/peripherals/tdm/TCM.bsv b/src/peripherals/tdm/TCM.bsv
index a9b48cdc22300177b53f1739ae4da2545a883d90..1ec417c601ea0c6e27eabda5c23666bb85bb7d81 100644 (file)
--- a/src/peripherals/tdm/TCM.bsv
+++ b/src/peripherals/tdm/TCM.bsv
@@ -14,7 +14,7 @@ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 package TCM;
        /*====== Porject imports ====*/
        import defined_types::*;
-       `include "defined_parameters.bsv"
+       `include "instance_defines.bsv"
        import Semi_FIFOF        :: *;
        import AXI4_Types   :: *;
        import AXI4_Fabric  :: *;

diff --git a/src/peripherals/uart/quart.bsv b/src/peripherals/uart/quart.bsv
index 392dcddff25d23d171868e3473e9de663a354868..f8aee3dde5d3860e57ad9f0b5a3e166b9f76b90a 100644 (file)
--- a/src/peripherals/uart/quart.bsv
+++ b/src/peripherals/uart/quart.bsv
@@ -56,21 +56,17 @@ package quart;
                                         (QUART_AXI4_Lite_Ifc);
 
     Uart16550_AXI4_Lite_Ifc uart <- mkUart16550(core_clock, core_reset);
-    //uart.pin_dsr_sync <= in; 
-    //uart.pin_ri_sync  <= in; 
-    //uart.pin_dcd_sync <= in; 
+
+    // ok set up CDC and dsr to 1, and Ring to 0. and otherwise ignore them
        rule rl_put;
-    Bit#(1) v1 = 1;
-    Bit#(1) v0 = 1;
-    uart.coe_rs232.dsr_in.put(1);
-    
-    uart.coe_rs232.dcd_in.put(1);
-    uart.coe_rs232.ri_in.put(0);
+        uart.coe_rs232.dsr_in.put(1);
+        uart.coe_rs232.dcd_in.put(1);
+        uart.coe_rs232.ri_in.put(0);
        endrule
     
-
+    // deliberately drop (ignore) this value
        rule rl_get;
-    let temp2 <- uart.coe_rs232.dtr_out.get;
+        let temp2 <- uart.coe_rs232.dtr_out.get;
        endrule
 
     interface out = interface QUART_out

diff --git a/src/peripherals/vme/Memory_vme_16.bsv b/src/peripherals/vme/Memory_vme_16.bsv
index 234cc5e51f07a3e26fe861665e66bb79a1734ed3..57c614fd3494dbc90240331ff521427ac58f598b 100644 (file)
--- a/src/peripherals/vme/Memory_vme_16.bsv
+++ b/src/peripherals/vme/Memory_vme_16.bsv
@@ -14,7 +14,7 @@ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 
 package Memory_vme_16;
        import defined_types::*;
-       `include "defined_parameters.bsv"
+       `include "instance_defines.bsv"
        import BRAMCore :: *;
  //       import TriState ::*;
 //     import DReg::*;

diff --git a/src/peripherals/vme/Memory_vme_32.bsv b/src/peripherals/vme/Memory_vme_32.bsv
index d5ee3b100481ebcdf7729a4774a1288fcdd9d754..d228c4761e6075a2cd84bb5982a8d72d5d759a3e 100644 (file)
--- a/src/peripherals/vme/Memory_vme_32.bsv
+++ b/src/peripherals/vme/Memory_vme_32.bsv
@@ -16,7 +16,7 @@ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 package Memory_vme_32;
        
        import defined_types::*;
-       `include "defined_parameters.bsv"
+       `include "instance_defines.bsv"
        import BRAMCore :: *;
        `include "vme_parameters.bsv"
 

diff --git a/src/peripherals/vme/Memory_vme_8.bsv b/src/peripherals/vme/Memory_vme_8.bsv
index e8bb898c6a06f26022ebe972b675767aeb3fd445..502ecd79a9f9bb97db9888cff335b11a911f65d0 100644 (file)
--- a/src/peripherals/vme/Memory_vme_8.bsv
+++ b/src/peripherals/vme/Memory_vme_8.bsv
@@ -15,7 +15,7 @@ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 
 package Memory_vme_8;
        import defined_types::*;
-       `include "defined_parameters.bsv"
+       `include "instance_defines.bsv"
        import BRAMCore :: *;
 
 

diff --git a/src/peripherals/vme/vme_top.bsv b/src/peripherals/vme/vme_top.bsv
index 502e0d86576513355b4a8cac22e637fc15a71a3f..bc0428f0b5ef9379e59461e9e5de06e4cac4ff8f 100644 (file)
--- a/src/peripherals/vme/vme_top.bsv
+++ b/src/peripherals/vme/vme_top.bsv
@@ -29,7 +29,7 @@ package vme_top;
 
        /*========= Project imports ======== */
        `include "vme_parameters.bsv"
-       `include "defined_parameters.bsv"
+       `include "instance_defines.bsv"
        import defined_types    ::*;
        import FIFOF                                    ::*;
        import vme_master :: *;

diff --git a/src/uncore/debug/DebugModule.bsv b/src/uncore/debug/DebugModule.bsv
index 75636cc62111081a71934d6230d93a53bea833cd..8b2807c5971bd284a0534e6e991e42ee13d65619 100644 (file)
--- a/src/uncore/debug/DebugModule.bsv
+++ b/src/uncore/debug/DebugModule.bsv
@@ -29,7 +29,7 @@ package DebugModule;
        import AXI4_Types::*;
        import AXI4_Fabric::*;
        `include "defines.bsv"
-       `include "defined_parameters.bsv"
+       `include "instance_defines.bsv"
        import defined_types::*;
        import core                     :: *;
        /*========================= */

diff --git a/src/uncore/tilelink/TLMemoryMap.bsv b/src/uncore/tilelink/TLMemoryMap.bsv
index 7c5823deab3576f9fe157c21b515738fae45efe3..542ff47924fbe14d90d709fdf196afa5b70e4f37 100644 (file)
--- a/src/uncore/tilelink/TLMemoryMap.bsv
+++ b/src/uncore/tilelink/TLMemoryMap.bsv
@@ -14,7 +14,7 @@ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 package MemoryMap;
        /*=== Project imports ==== */
        import defined_types::*;
-       `include "defined_parameters.bsv"
+       `include "instance_defines.bsv"
        /*========================= */