From 4281aa9ba88cb0aea5efef17ff324ca0ffac86fc Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 2 Aug 2018 12:32:01 +0100 Subject: [PATCH] add dummy clock register for now --- src/peripherals/sdram/sdr_top.bsv | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/peripherals/sdram/sdr_top.bsv b/src/peripherals/sdram/sdr_top.bsv index d886fd5..781dd76 100644 --- a/src/peripherals/sdram/sdr_top.bsv +++ b/src/peripherals/sdram/sdr_top.bsv @@ -245,10 +245,8 @@ endfunction (*synthesize*) -module mksdr_axi4_slave#(Clock clk0) (Ifc_sdr_slave); +module mksdr_axi4_slave#(Clock clk0, Reset rst0) (Ifc_sdr_slave); - Reset rst0 <- mkAsyncResetFromCR (0, clk0); - Reg#(Bit#(9)) rg_delay_count <- mkReg(0,clocked_by clk0, reset_by rst0); Reg#(Bit#(9)) rg_rd_actual_len <- mkReg(0,clocked_by clk0, reset_by rst0); Reg#(bit) rg_app_req <- mkDReg(0,clocked_by clk0, reset_by rst0); @@ -341,6 +339,9 @@ module mksdr_axi4_slave#(Clock clk0) (Ifc_sdr_slave); AXI4_Slave_Xactor_IFC #(`PADDR, `Reg_width, `USERSPACE) s_xactor_cntrl_reg <- mkAXI4_Slave_Xactor; Ifc_sdram sdr_cntrl <- mksdrc_top(clocked_by clk0, reset_by rst0); + // TODO remove the following when clock to bit type conversion is done + Reg#(Bit#(1)) rg_dummy <- mkReg(0, clocked_by clk0, reset_by rst0); + function Action fn_wr_cntrl_reg(Bit#(64) data, Bit#(8) address); action case(address) @@ -828,7 +829,7 @@ module mksdr_axi4_slave#(Clock clk0) (Ifc_sdr_slave); interface osdr_clock = interface Get method ActionValue#(Bit#(1)) get; - return ?; + return rg_dummy; endmethod endinterface; endinterface -- 2.30.2