src/main/scala/devices/gpio/GPIO.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.gpio
   3
   4 import Chisel._
   5 import sifive.blocks.devices.pinctrl.{PinCtrl, Pin, BasePin, EnhancedPin, EnhancedPinCtrl}
   6 import freechips.rocketchip.config.Parameters
   7 import freechips.rocketchip.regmapper._
   8 import freechips.rocketchip.tilelink._
   9 import freechips.rocketchip.util.{AsyncResetRegVec, GenericParameterizedBundle}
  10
  11 case class GPIOParams(address: BigInt, width: Int, includeIOF: Boolean = false)
  12
  13 // This is the actual IOF interface.pa
  14 // Add a valid bit to indicate whether
  15 // there is something actually connected
  16 // to this.
  17 class IOFCtrl extends PinCtrl {
  18   val valid = Bool()
  19 }
  20
  21 // By default,
  22 object IOFCtrl {
  23   def apply(): IOFCtrl = {
  24     val iof = Wire(new IOFCtrl())
  25     iof.valid := Bool(false)
  26     iof.oval  := Bool(false)
  27     iof.oe    := Bool(false)
  28     iof.ie    := Bool(false)
  29     iof
  30   }
  31 }
  32
  33 // Package up the inputs and outputs
  34 // for the IOF
  35 class IOFPin extends Pin {
  36   val o  = new IOFCtrl().asOutput
  37
  38   def default(): Unit = {
  39     this.o.oval  := Bool(false)
  40     this.o.oe    := Bool(false)
  41     this.o.ie    := Bool(false)
  42     this.o.valid := Bool(false)
  43   }
  44
  45   def inputPin(pue: Bool = Bool(false) /*ignored*/): Bool = {
  46     this.o.oval := Bool(false)
  47     this.o.oe   := Bool(false)
  48     this.o.ie   := Bool(true)
  49     this.i.ival
  50   }
  51   def outputPin(signal: Bool,
  52     pue: Bool = Bool(false), /*ignored*/
  53     ds: Bool = Bool(false), /*ignored*/
  54     ie: Bool = Bool(false)
  55   ): Unit = {
  56     this.o.oval := signal
  57     this.o.oe   := Bool(true)
  58     this.o.ie   := ie
  59   }
  60 }
  61
  62 // Connect both the i and o side of the pin,
  63 // and drive the valid signal for the IOF.
  64 object BasePinToIOF {
  65   def apply(pin: BasePin, iof: IOFPin): Unit = {
  66     iof <> pin
  67     iof.o.valid := Bool(true)
  68   }
  69 }
  70
  71 // This is sort of weird because
  72 // the IOF end up at the RocketChipTop
  73 // level, and we have to do the pinmux
  74 // outside of RocketChipTop.
  75
  76 class GPIOPortIO(c: GPIOParams) extends GenericParameterizedBundle(c) {
  77   val pins = Vec(c.width, new EnhancedPin())
  78   val iof_0 = if (c.includeIOF) Some(Vec(c.width, new IOFPin).flip) else None
  79   val iof_1 = if (c.includeIOF) Some(Vec(c.width, new IOFPin).flip) else None
  80 }
  81
  82 // It would be better if the IOF were here and
  83 // we could do the pinmux inside.
  84 trait HasGPIOBundleContents extends Bundle {
  85   val params: GPIOParams
  86   val port = new GPIOPortIO(params)
  87 }
  88
  89 trait HasGPIOModuleContents extends Module with HasRegMap {
  90   val io: HasGPIOBundleContents
  91   val params: GPIOParams
  92   val c = params
  93
  94   //--------------------------------------------------
  95   // CSR Declarations
  96   // -------------------------------------------------
  97
  98   // SW Control only.
  99   val portReg = Reg(init = UInt(0, c.width))
 100
 101   val oeReg  = Module(new AsyncResetRegVec(c.width, 0))
 102   val pueReg = Module(new AsyncResetRegVec(c.width, 0))
 103   val dsReg  = Reg(init = UInt(0, c.width))
 104   val ieReg  = Module(new AsyncResetRegVec(c.width, 0))
 105
 106   // Synchronize Input to get valueReg
 107   val inVal = Wire(UInt(0, width=c.width))
 108   inVal := Vec(io.port.pins.map(_.i.ival)).asUInt
 109   val inSyncReg  = ShiftRegister(inVal, 3)
 110   val valueReg   = Reg(init = UInt(0, c.width), next = inSyncReg)
 111
 112   // Interrupt Configuration
 113   val highIeReg = Reg(init = UInt(0, c.width))
 114   val lowIeReg  = Reg(init = UInt(0, c.width))
 115   val riseIeReg = Reg(init = UInt(0, c.width))
 116   val fallIeReg = Reg(init = UInt(0, c.width))
 117   val highIpReg = Reg(init = UInt(0, c.width))
 118   val lowIpReg  = Reg(init = UInt(0, c.width))
 119   val riseIpReg = Reg(init = UInt(0, c.width))
 120   val fallIpReg = Reg(init = UInt(0, c.width))
 121
 122   // HW IO Function
 123   val iofEnReg  = Module(new AsyncResetRegVec(c.width, 0))
 124   val iofSelReg = Reg(init = UInt(0, c.width))
 125
 126   // Invert Output
 127   val xorReg    = Reg(init = UInt(0, c.width))
 128
 129   //--------------------------------------------------
 130   // CSR Access Logic (most of this section is boilerplate)
 131   // -------------------------------------------------
 132
 133   val rise = ~valueReg & inSyncReg;
 134   val fall = valueReg & ~inSyncReg;
 135
 136   val iofEnFields =  if (c.includeIOF) (Seq(RegField.rwReg(c.width, iofEnReg.io))) else (Seq(RegField(c.width)))
 137   val iofSelFields = if (c.includeIOF) (Seq(RegField(c.width, iofSelReg))) else (Seq(RegField(c.width)))
 138
 139
 140   // Note that these are out of order.
 141   regmap(
 142     GPIOCtrlRegs.value     -> Seq(RegField.r(c.width, valueReg)),
 143     GPIOCtrlRegs.output_en -> Seq(RegField.rwReg(c.width, oeReg.io)),
 144     GPIOCtrlRegs.rise_ie   -> Seq(RegField(c.width, riseIeReg)),
 145     GPIOCtrlRegs.rise_ip   -> Seq(RegField.w1ToClear(c.width, riseIpReg, rise)),
 146     GPIOCtrlRegs.fall_ie   -> Seq(RegField(c.width, fallIeReg)),
 147     GPIOCtrlRegs.fall_ip   -> Seq(RegField.w1ToClear(c.width, fallIpReg, fall)),
 148     GPIOCtrlRegs.high_ie   -> Seq(RegField(c.width, highIeReg)),
 149     GPIOCtrlRegs.high_ip   -> Seq(RegField.w1ToClear(c.width, highIpReg, valueReg)),
 150     GPIOCtrlRegs.low_ie    -> Seq(RegField(c.width, lowIeReg)),
 151     GPIOCtrlRegs.low_ip    -> Seq(RegField.w1ToClear(c.width,lowIpReg, ~valueReg)),
 152     GPIOCtrlRegs.port      -> Seq(RegField(c.width, portReg)),
 153     GPIOCtrlRegs.pullup_en -> Seq(RegField.rwReg(c.width, pueReg.io)),
 154     GPIOCtrlRegs.iof_en    -> iofEnFields,
 155     GPIOCtrlRegs.iof_sel   -> iofSelFields,
 156     GPIOCtrlRegs.drive     -> Seq(RegField(c.width, dsReg)),
 157     GPIOCtrlRegs.input_en  -> Seq(RegField.rwReg(c.width, ieReg.io)),
 158     GPIOCtrlRegs.out_xor   -> Seq(RegField(c.width, xorReg))
 159
 160   )
 161
 162   //--------------------------------------------------
 163   // Actual Pinmux
 164   // -------------------------------------------------
 165
 166   val swPinCtrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
 167
 168   // This strips off the valid.
 169   val iof0Ctrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
 170   val iof1Ctrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
 171
 172   val iofCtrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
 173   val iofPlusSwPinCtrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
 174
 175   for (pin <- 0 until c.width) {
 176
 177     // Software Pin Control
 178     swPinCtrl(pin).pue    := pueReg.io.q(pin)
 179     swPinCtrl(pin).oval   := portReg(pin)
 180     swPinCtrl(pin).oe     := oeReg.io.q(pin)
 181     swPinCtrl(pin).ds     := dsReg(pin)
 182     swPinCtrl(pin).ie     := ieReg.io.q(pin)
 183
 184     val pre_xor = Wire(new EnhancedPinCtrl())
 185
 186     if (c.includeIOF) {
 187       // Allow SW Override for invalid inputs.
 188       iof0Ctrl(pin)      <> swPinCtrl(pin)
 189       when (io.port.iof_0.get(pin).o.valid) {
 190         iof0Ctrl(pin)    <> io.port.iof_0.get(pin).o
 191       }
 192
 193       iof1Ctrl(pin)      <> swPinCtrl(pin)
 194       when (io.port.iof_1.get(pin).o.valid) {
 195         iof1Ctrl(pin)    <> io.port.iof_1.get(pin).o
 196       }
 197
 198       // Select IOF 0 vs. IOF 1.
 199       iofCtrl(pin)       <> Mux(iofSelReg(pin), iof1Ctrl(pin), iof0Ctrl(pin))
 200
 201       // Allow SW Override for things IOF doesn't control.
 202       iofPlusSwPinCtrl(pin) <> swPinCtrl(pin)
 203       iofPlusSwPinCtrl(pin) <> iofCtrl(pin)
 204
 205       // Final XOR & Pin Control
 206       pre_xor  := Mux(iofEnReg.io.q(pin), iofPlusSwPinCtrl(pin), swPinCtrl(pin))
 207     } else {
 208       pre_xor := swPinCtrl(pin)
 209     }
 210
 211     io.port.pins(pin).o      := pre_xor
 212     io.port.pins(pin).o.oval := pre_xor.oval ^ xorReg(pin)
 213
 214     // Generate Interrupts
 215     interrupts(pin) := (riseIpReg(pin) & riseIeReg(pin)) |
 216                          (fallIpReg(pin) & fallIeReg(pin)) |
 217                          (highIpReg(pin) & highIeReg(pin)) |
 218                          (lowIpReg(pin) & lowIeReg(pin))
 219
 220     if (c.includeIOF) {
 221       // Send Value to all consumers
 222       io.port.iof_0.get(pin).i.ival := inSyncReg(pin)
 223       io.port.iof_1.get(pin).i.ival := inSyncReg(pin)
 224     }
 225   }
 226 }
 227
 228 // Magic TL2 Incantation to create a TL2 Slave
 229 class TLGPIO(w: Int, c: GPIOParams)(implicit p: Parameters)
 230   extends TLRegisterRouter(c.address, "gpio", Seq("sifive,gpio0"), interrupts = c.width, beatBytes = w)(
 231   new TLRegBundle(c, _)    with HasGPIOBundleContents)(
 232   new TLRegModule(c, _, _) with HasGPIOModuleContents)