src/main/scala/devices/gpio/GPIO.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.gpio
   3
   4 import Chisel._
   5 import chisel3.experimental.MultiIOModule
   6 import sifive.blocks.devices.pinctrl.{PinCtrl, Pin, BasePin, EnhancedPin, EnhancedPinCtrl}
   7 import freechips.rocketchip.config.Parameters
   8 import freechips.rocketchip.util.SynchronizerShiftReg
   9 import freechips.rocketchip.regmapper._
  10 import freechips.rocketchip.tilelink._
  11 import freechips.rocketchip.util.{AsyncResetRegVec, GenericParameterizedBundle}
  12
  13 case class GPIOParams(address: BigInt, width: Int, includeIOF: Boolean = false)
  14
  15 // This is the actual IOF interface.pa
  16 // Add a valid bit to indicate whether
  17 // there is something actually connected
  18 // to this.
  19 class IOFCtrl extends PinCtrl {
  20   val valid = Bool()
  21 }
  22
  23 // By default,
  24 object IOFCtrl {
  25   def apply(): IOFCtrl = {
  26     val iof = Wire(new IOFCtrl())
  27     iof.valid := Bool(false)
  28     iof.oval  := Bool(false)
  29     iof.oe    := Bool(false)
  30     iof.ie    := Bool(false)
  31     iof
  32   }
  33 }
  34
  35 // Package up the inputs and outputs
  36 // for the IOF
  37 class IOFPin extends Pin {
  38   val o  = new IOFCtrl().asOutput
  39
  40   def default(): Unit = {
  41     this.o.oval  := Bool(false)
  42     this.o.oe    := Bool(false)
  43     this.o.ie    := Bool(false)
  44     this.o.valid := Bool(false)
  45   }
  46
  47   def inputPin(pue: Bool = Bool(false) /*ignored*/): Bool = {
  48     this.o.oval := Bool(false)
  49     this.o.oe   := Bool(false)
  50     this.o.ie   := Bool(true)
  51     this.i.ival
  52   }
  53   def outputPin(signal: Bool,
  54     pue: Bool = Bool(false), /*ignored*/
  55     ds: Bool = Bool(false), /*ignored*/
  56     ie: Bool = Bool(false)
  57   ): Unit = {
  58     this.o.oval := signal
  59     this.o.oe   := Bool(true)
  60     this.o.ie   := ie
  61   }
  62 }
  63
  64 // Connect both the i and o side of the pin,
  65 // and drive the valid signal for the IOF.
  66 object BasePinToIOF {
  67   def apply(pin: BasePin, iof: IOFPin): Unit = {
  68     iof <> pin
  69     iof.o.valid := Bool(true)
  70   }
  71 }
  72
  73 // This is sort of weird because
  74 // the IOF end up at the RocketChipTop
  75 // level, and we have to do the pinmux
  76 // outside of RocketChipTop.
  77
  78 class GPIOPortIO(c: GPIOParams) extends GenericParameterizedBundle(c) {
  79   val pins = Vec(c.width, new EnhancedPin())
  80   val iof_0 = if (c.includeIOF) Some(Vec(c.width, new IOFPin).flip) else None
  81   val iof_1 = if (c.includeIOF) Some(Vec(c.width, new IOFPin).flip) else None
  82 }
  83
  84 // It would be better if the IOF were here and
  85 // we could do the pinmux inside.
  86 trait HasGPIOBundleContents extends Bundle {
  87   def params: GPIOParams
  88   val port = new GPIOPortIO(params)
  89 }
  90
  91 trait HasGPIOModuleContents extends MultiIOModule with HasRegMap {
  92   val io: HasGPIOBundleContents
  93   val params: GPIOParams
  94   val c = params
  95
  96   //--------------------------------------------------
  97   // CSR Declarations
  98   // -------------------------------------------------
  99
 100   // SW Control only.
 101   val portReg = Reg(init = UInt(0, c.width))
 102
 103   val oeReg  = Module(new AsyncResetRegVec(c.width, 0))
 104   val pueReg = Module(new AsyncResetRegVec(c.width, 0))
 105   val dsReg  = Reg(init = UInt(0, c.width))
 106   val ieReg  = Module(new AsyncResetRegVec(c.width, 0))
 107
 108   // Synchronize Input to get valueReg
 109   val inVal = Wire(UInt(0, width=c.width))
 110   inVal := Vec(io.port.pins.map(_.i.ival)).asUInt
 111   val inSyncReg  = SynchronizerShiftReg(inVal, 3, Some("inSyncReg"))
 112   val valueReg   = Reg(init = UInt(0, c.width), next = inSyncReg)
 113
 114   // Interrupt Configuration
 115   val highIeReg = Reg(init = UInt(0, c.width))
 116   val lowIeReg  = Reg(init = UInt(0, c.width))
 117   val riseIeReg = Reg(init = UInt(0, c.width))
 118   val fallIeReg = Reg(init = UInt(0, c.width))
 119   val highIpReg = Reg(init = UInt(0, c.width))
 120   val lowIpReg  = Reg(init = UInt(0, c.width))
 121   val riseIpReg = Reg(init = UInt(0, c.width))
 122   val fallIpReg = Reg(init = UInt(0, c.width))
 123
 124   // HW IO Function
 125   val iofEnReg  = Module(new AsyncResetRegVec(c.width, 0))
 126   val iofSelReg = Reg(init = UInt(0, c.width))
 127
 128   // Invert Output
 129   val xorReg    = Reg(init = UInt(0, c.width))
 130
 131   //--------------------------------------------------
 132   // CSR Access Logic (most of this section is boilerplate)
 133   // -------------------------------------------------
 134
 135   val rise = ~valueReg & inSyncReg;
 136   val fall = valueReg & ~inSyncReg;
 137
 138   val iofEnFields =  if (c.includeIOF) (Seq(RegField.rwReg(c.width, iofEnReg.io))) else (Seq(RegField(c.width)))
 139   val iofSelFields = if (c.includeIOF) (Seq(RegField(c.width, iofSelReg))) else (Seq(RegField(c.width)))
 140
 141
 142   // Note that these are out of order.
 143   regmap(
 144     GPIOCtrlRegs.value     -> Seq(RegField.r(c.width, valueReg)),
 145     GPIOCtrlRegs.output_en -> Seq(RegField.rwReg(c.width, oeReg.io)),
 146     GPIOCtrlRegs.rise_ie   -> Seq(RegField(c.width, riseIeReg)),
 147     GPIOCtrlRegs.rise_ip   -> Seq(RegField.w1ToClear(c.width, riseIpReg, rise)),
 148     GPIOCtrlRegs.fall_ie   -> Seq(RegField(c.width, fallIeReg)),
 149     GPIOCtrlRegs.fall_ip   -> Seq(RegField.w1ToClear(c.width, fallIpReg, fall)),
 150     GPIOCtrlRegs.high_ie   -> Seq(RegField(c.width, highIeReg)),
 151     GPIOCtrlRegs.high_ip   -> Seq(RegField.w1ToClear(c.width, highIpReg, valueReg)),
 152     GPIOCtrlRegs.low_ie    -> Seq(RegField(c.width, lowIeReg)),
 153     GPIOCtrlRegs.low_ip    -> Seq(RegField.w1ToClear(c.width,lowIpReg, ~valueReg)),
 154     GPIOCtrlRegs.port      -> Seq(RegField(c.width, portReg)),
 155     GPIOCtrlRegs.pullup_en -> Seq(RegField.rwReg(c.width, pueReg.io)),
 156     GPIOCtrlRegs.iof_en    -> iofEnFields,
 157     GPIOCtrlRegs.iof_sel   -> iofSelFields,
 158     GPIOCtrlRegs.drive     -> Seq(RegField(c.width, dsReg)),
 159     GPIOCtrlRegs.input_en  -> Seq(RegField.rwReg(c.width, ieReg.io)),
 160     GPIOCtrlRegs.out_xor   -> Seq(RegField(c.width, xorReg))
 161
 162   )
 163
 164   //--------------------------------------------------
 165   // Actual Pinmux
 166   // -------------------------------------------------
 167
 168   val swPinCtrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
 169
 170   // This strips off the valid.
 171   val iof0Ctrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
 172   val iof1Ctrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
 173
 174   val iofCtrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
 175   val iofPlusSwPinCtrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
 176
 177   for (pin <- 0 until c.width) {
 178
 179     // Software Pin Control
 180     swPinCtrl(pin).pue    := pueReg.io.q(pin)
 181     swPinCtrl(pin).oval   := portReg(pin)
 182     swPinCtrl(pin).oe     := oeReg.io.q(pin)
 183     swPinCtrl(pin).ds     := dsReg(pin)
 184     swPinCtrl(pin).ie     := ieReg.io.q(pin)
 185
 186     val pre_xor = Wire(new EnhancedPinCtrl())
 187
 188     if (c.includeIOF) {
 189       // Allow SW Override for invalid inputs.
 190       iof0Ctrl(pin)      <> swPinCtrl(pin)
 191       when (io.port.iof_0.get(pin).o.valid) {
 192         iof0Ctrl(pin)    <> io.port.iof_0.get(pin).o
 193       }
 194
 195       iof1Ctrl(pin)      <> swPinCtrl(pin)
 196       when (io.port.iof_1.get(pin).o.valid) {
 197         iof1Ctrl(pin)    <> io.port.iof_1.get(pin).o
 198       }
 199
 200       // Select IOF 0 vs. IOF 1.
 201       iofCtrl(pin)       <> Mux(iofSelReg(pin), iof1Ctrl(pin), iof0Ctrl(pin))
 202
 203       // Allow SW Override for things IOF doesn't control.
 204       iofPlusSwPinCtrl(pin) <> swPinCtrl(pin)
 205       iofPlusSwPinCtrl(pin) <> iofCtrl(pin)
 206
 207       // Final XOR & Pin Control
 208       pre_xor  := Mux(iofEnReg.io.q(pin), iofPlusSwPinCtrl(pin), swPinCtrl(pin))
 209     } else {
 210       pre_xor := swPinCtrl(pin)
 211     }
 212
 213     io.port.pins(pin).o      := pre_xor
 214     io.port.pins(pin).o.oval := pre_xor.oval ^ xorReg(pin)
 215
 216     // Generate Interrupts
 217     interrupts(pin) := (riseIpReg(pin) & riseIeReg(pin)) |
 218                          (fallIpReg(pin) & fallIeReg(pin)) |
 219                          (highIpReg(pin) & highIeReg(pin)) |
 220                          (lowIpReg(pin) & lowIeReg(pin))
 221
 222     if (c.includeIOF) {
 223       // Send Value to all consumers
 224       io.port.iof_0.get(pin).i.ival := inSyncReg(pin)
 225       io.port.iof_1.get(pin).i.ival := inSyncReg(pin)
 226     }
 227   }
 228 }
 229
 230 // Magic TL2 Incantation to create a TL2 Slave
 231 class TLGPIO(w: Int, c: GPIOParams)(implicit p: Parameters)
 232   extends TLRegisterRouter(c.address, "gpio", Seq("sifive,gpio0"), interrupts = c.width, beatBytes = w)(
 233   new TLRegBundle(c, _)    with HasGPIOBundleContents)(
 234   new TLRegModule(c, _, _) with HasGPIOModuleContents)