src/main/scala/devices/gpio/JTAG.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.gpio
   3
   4 import Chisel._
   5
   6 // ------------------------------------------------------------
   7 // SPI, UART, etc are with their
   8 // respective packages,
   9 // This file is for those that don't seem to have a good place
  10 // to put them otherwise.
  11 // ------------------------------------------------------------
  12
  13 import config._
  14 import junctions.{JTAGIO}
  15
  16 class JTAGPinsIO extends Bundle {
  17
  18   val TCK    = new GPIOPin()
  19   val TMS    = new GPIOPin()
  20   val TDI    = new GPIOPin()
  21   val TDO    = new GPIOPin()
  22   val TRST_n = new GPIOPin()
  23
  24 }
  25
  26 class JTAGGPIOPort(drvTdo: Boolean = false)(implicit p: Parameters) extends Module {
  27
  28   val io = new Bundle {
  29     val jtag = new JTAGIO(drvTdo)
  30     val pins = new JTAGPinsIO()
  31   }
  32
  33   io.jtag.TCK  := GPIOInputPinCtrl(io.pins.TCK, pue = Bool(true)).asClock
  34   io.jtag.TMS  := GPIOInputPinCtrl(io.pins.TMS, pue = Bool(true))
  35   io.jtag.TDI  := GPIOInputPinCtrl(io.pins.TDI, pue = Bool(true))
  36   io.jtag.TRST := ~GPIOInputPinCtrl(io.pins.TRST_n, pue = Bool(true))
  37
  38   GPIOOutputPinCtrl(io.pins.TDO, io.jtag.TDO)
  39   if (drvTdo) {
  40     io.pins.TDO.o.oe := io.jtag.DRV_TDO.get
  41   }
  42
  43 }