1 // See LICENSE for license details.
2 package sifive.blocks.devices.i2c
8 import uncore.tilelink2._
9 import rocketchip.PeripheryBusConfig
10 import util.AsyncResetRegVec
11 import sifive.blocks.devices.gpio.{GPIOPinCtrl}
13 case class I2CConfig(address: BigInt)
15 trait HasI2CParameters {
16 implicit val p: Parameters
21 class I2CPin extends Bundle {
23 val out = Bool(OUTPUT)
27 class I2CPort extends Bundle {
32 trait I2CBundle extends Bundle with HasI2CParameters {
33 val port = new I2CPort
36 trait I2CModule extends Module with HasI2CParameters with HasRegMap {
39 val I2C_CMD_NOP = UInt(0x00)
40 val I2C_CMD_START = UInt(0x01)
41 val I2C_CMD_STOP = UInt(0x02)
42 val I2C_CMD_WRITE = UInt(0x04)
43 val I2C_CMD_READ = UInt(0x08)
45 class PrescalerBundle extends Bundle{
50 class ControlBundle extends Bundle{
53 val reserved = UInt(6.W)
56 class CommandBundle extends Bundle{
62 val reserved = UInt(2.W)
66 class StatusBundle extends Bundle{
67 val receivedAck = Bool() // received aknowledge from slave
70 val reserved = UInt(3.W)
71 val transferInProgress = Bool()
75 // control state visible to SW/driver
76 val prescaler = Reg(init = (new PrescalerBundle).fromBits(0xFFFF.U))
77 val control = Reg(init = (new ControlBundle).fromBits(0.U))
78 val transmitData = Reg(init = UInt(0, 8.W))
79 val receivedData = Reg(init = UInt(0, 8.W))
80 val cmd = Reg(init = (new CommandBundle).fromBits(0.U))
81 val status = Reg(init = (new StatusBundle).fromBits(0.U))
84 //////// Bit level ////////
86 io.port.scl.out := false.B // i2c clock line output
87 io.port.sda.out := false.B // i2c data line output
89 // filter SCL and SDA signals; (attempt to) remove glitches
90 val filterCnt = Reg(init = UInt(0, 14.W))
91 when ( !control.coreEn ) {
93 } .elsewhen (!(filterCnt.orR)) {
94 filterCnt := Cat(prescaler.hi, prescaler.lo) >> 2 //16x I2C bus frequency
96 filterCnt := filterCnt - 1.U
99 val fSCL = Reg(init = UInt(0x7, 3.W))
100 val fSDA = Reg(init = UInt(0x7, 3.W))
101 when (!(filterCnt.orR)) {
102 fSCL := Cat(fSCL, io.port.scl.in)
103 fSDA := Cat(fSDA, io.port.sda.in)
106 val sSCL = Reg(init = true.B, next = (new Majority(fSCL.toBools.toSet)).out)
107 val sSDA = Reg(init = true.B, next = (new Majority(fSDA.toBools.toSet)).out)
109 val dSCL = Reg(init = true.B, next = sSCL)
110 val dSDA = Reg(init = true.B, next = sSDA)
112 val dSCLOen = Reg(next = io.port.scl.oe) // delayed scl_oen
114 // detect start condition => detect falling edge on SDA while SCL is high
115 // detect stop condition => detect rising edge on SDA while SCL is high
116 val startCond = Reg(init = false.B, next = !sSDA && dSDA && sSCL)
117 val stopCond = Reg(init = false.B, next = sSDA && !dSDA && sSCL)
119 // master drives SCL high, but another master pulls it low
120 // master start counting down its low cycle now (clock synchronization)
121 val sclSync = dSCL && !sSCL && io.port.scl.oe
123 // slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low
124 // slave_wait remains asserted until the slave releases SCL
125 val slaveWait = Reg(init = false.B)
126 slaveWait := (io.port.scl.oe && !dSCLOen && !sSCL) || (slaveWait && !sSCL)
128 val clkEn = Reg(init = true.B) // clock generation signals
129 val cnt = Reg(init = UInt(0, 16.W)) // clock divider counter (synthesis)
131 // generate clk enable signal
132 when (!(cnt.orR) || !control.coreEn || sclSync ) {
133 cnt := Cat(prescaler.hi, prescaler.lo)
136 .elsewhen (slaveWait) {
144 val sclOen = Reg(init = true.B)
145 io.port.scl.oe := sclOen
147 val sdaOen = Reg(init = true.B)
148 io.port.sda.oe := sdaOen
150 val sdaChk = Reg(init = false.B) // check SDA output (Multi-master arbitration)
152 val transmitBit = Reg(init = false.B)
153 val receivedBit = Reg(Bool())
154 when (sSCL && !dSCL) {
158 val bitCmd = Reg(init = UInt(0, 4.W)) // command (from byte controller)
159 val bitCmdStop = Reg(init = false.B)
161 bitCmdStop := bitCmd === I2C_CMD_STOP
163 val bitCmdAck = Reg(init = false.B)
166 s_bit_start_a :: s_bit_start_b :: s_bit_start_c :: s_bit_start_d :: s_bit_start_e ::
167 s_bit_stop_a :: s_bit_stop_b :: s_bit_stop_c :: s_bit_stop_d ::
168 s_bit_rd_a :: s_bit_rd_b :: s_bit_rd_c :: s_bit_rd_d ::
169 s_bit_wr_a :: s_bit_wr_b :: s_bit_wr_c :: s_bit_wr_d :: Nil) = Enum(UInt(), 18)
170 val bitState = Reg(init = s_bit_idle)
172 val arbLost = Reg(init = false.B, next = (sdaChk && !sSDA && sdaOen) | ((bitState === s_bit_idle) && stopCond && !bitCmdStop))
176 bitState := s_bit_idle
189 is (I2C_CMD_START) { bitState := s_bit_start_a }
190 is (I2C_CMD_STOP) { bitState := s_bit_stop_a }
191 is (I2C_CMD_WRITE) { bitState := s_bit_wr_a }
192 is (I2C_CMD_READ) { bitState := s_bit_rd_a }
198 bitState := s_bit_start_b
204 bitState := s_bit_start_c
210 bitState := s_bit_start_d
216 bitState := s_bit_start_e
222 bitState := s_bit_idle
230 bitState := s_bit_stop_b
236 bitState := s_bit_stop_c
242 bitState := s_bit_stop_d
248 bitState := s_bit_idle
256 bitState := s_bit_rd_b
262 bitState := s_bit_rd_c
268 bitState := s_bit_rd_d
274 bitState := s_bit_idle
282 bitState := s_bit_wr_b
284 sdaOen := transmitBit
288 bitState := s_bit_wr_c
290 sdaOen := transmitBit
294 bitState := s_bit_wr_d
296 sdaOen := transmitBit
300 bitState := s_bit_idle
303 sdaOen := transmitBit
311 //////// Byte level ///////
312 val load = Reg(init = false.B) // load shift register
313 val shift = Reg(init = false.B) // shift shift register
314 val cmdAck = Reg(init = false.B) // also done
315 val receivedAck = Reg(init = false.B) // from I2C slave
316 val go = (cmd.read | cmd.write | cmd.stop) & !cmdAck
318 val bitCnt = Reg(init = UInt(0, 3.W))
323 bitCnt := bitCnt - 1.U
325 val bitCntDone = !(bitCnt.orR)
327 // receivedData is used as shift register directly
329 receivedData := transmitData
332 receivedData := Cat(receivedData, receivedBit)
335 val (s_byte_idle :: s_byte_start :: s_byte_read :: s_byte_write :: s_byte_ack :: s_byte_stop :: Nil) = Enum(UInt(), 6)
336 val byteState = Reg(init = s_byte_idle)
339 bitCmd := I2C_CMD_NOP
340 transmitBit := false.B
344 byteState := s_byte_idle
345 receivedAck := false.B
348 transmitBit := receivedData(7)
357 byteState := s_byte_start
358 bitCmd := I2C_CMD_START
360 .elsewhen (cmd.read) {
361 byteState := s_byte_read
362 bitCmd := I2C_CMD_READ
364 .elsewhen (cmd.write) {
365 byteState := s_byte_write
366 bitCmd := I2C_CMD_WRITE
369 byteState := s_byte_stop
370 bitCmd := I2C_CMD_STOP
379 byteState := s_byte_read
380 bitCmd := I2C_CMD_READ
383 byteState := s_byte_write
384 bitCmd := I2C_CMD_WRITE
393 byteState := s_byte_ack
394 bitCmd := I2C_CMD_READ
397 byteState := s_byte_write
398 bitCmd := I2C_CMD_WRITE
406 byteState := s_byte_ack
407 bitCmd := I2C_CMD_WRITE
410 byteState := s_byte_read
411 bitCmd := I2C_CMD_READ
415 transmitBit := cmd.ack
421 byteState := s_byte_stop
422 bitCmd := I2C_CMD_STOP
425 byteState := s_byte_idle
426 bitCmd := I2C_CMD_NOP
428 // generate command acknowledge signal
432 // assign ack_out output to bit_controller_rxd (contains last received bit)
433 receivedAck := receivedBit
435 transmitBit := true.B
438 transmitBit := cmd.ack
443 byteState := s_byte_idle
444 bitCmd := I2C_CMD_NOP
446 // assign ack_out output to bit_controller_rxd (contains last received bit)
454 //////// Top level ////////
456 // hack: b/c the same register offset is used to write cmd and read status
457 val nextCmd = Wire(UInt(8.W))
458 nextCmd := cmd.asUInt
459 cmd := (new CommandBundle).fromBits(nextCmd)
461 when (cmdAck || arbLost) {
462 cmd.start := false.B // clear command bits when done
463 cmd.stop := false.B // or when aribitration lost
467 cmd.irqAck := false.B // clear IRQ_ACK bit (essentially 1 cycle pulse b/c it is overwritten by regmap below)
469 status.receivedAck := receivedAck
471 status.busy := false.B
473 .elsewhen (startCond) {
474 status.busy := true.B
478 status.arbLost := true.B
480 .elsewhen (cmd.start) {
481 status.arbLost := false.B
483 status.transferInProgress := cmd.read || cmd.write
484 status.irqFlag := (cmdAck || arbLost || status.irqFlag) && !cmd.irqAck
488 I2CCtrlRegs.prescaler_lo -> Seq(RegField(8, prescaler.lo)),
489 I2CCtrlRegs.prescaler_hi -> Seq(RegField(8, prescaler.hi)),
490 I2CCtrlRegs.control -> control.elements.map{ case(name, e) => RegField(e.getWidth, e.asInstanceOf[UInt]) }.toSeq,
491 I2CCtrlRegs.data -> Seq(RegField(8, r = RegReadFn(receivedData), w = RegWriteFn(transmitData))),
492 I2CCtrlRegs.cmd_status -> Seq(RegField(8, r = RegReadFn(status.asUInt), w = RegWriteFn(nextCmd)))
495 // tie off unused bits
496 control.reserved := 0.U
498 status.reserved := 0.U
500 interrupts(0) := status.irqFlag & control.intEn
503 // Copied from UART.scala
504 class Majority(in: Set[Bool]) {
505 private val n = (in.size >> 1) + 1
506 private val clauses = in.subsets(n).map(_.reduce(_ && _))
507 val out = clauses.reduce(_ || _)
511 // Magic TL2 Incantation to create a TL2 Slave
512 class TLI2C(c: I2CConfig)(implicit p: Parameters)
513 extends TLRegisterRouter(c.address, interrupts = 1, beatBytes = p(PeripheryBusConfig).beatBytes)(
514 new TLRegBundle(c, _) with I2CBundle)(
515 new TLRegModule(c, _, _) with I2CModule)