src/main/scala/devices/i2c/I2CPeriphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.i2c
   3
   4 import Chisel._
   5 import config.Field
   6 import diplomacy.LazyModule
   7 import rocketchip.{HasTopLevelNetworks,HasTopLevelNetworksBundle,HasTopLevelNetworksModule}
   8 import uncore.tilelink2.TLFragmenter
   9
  10 case object PeripheryI2CKey extends Field[Seq[I2CParams]]
  11
  12 trait HasPeripheryI2C extends HasTopLevelNetworks {
  13   val i2cParams = p(PeripheryI2CKey)
  14   val i2c = i2cParams map { params =>
  15     val i2c = LazyModule(new TLI2C(peripheryBusBytes, params))
  16     i2c.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
  17     intBus.intnode := i2c.intnode
  18     i2c
  19   }
  20 }
  21
  22 trait HasPeripheryI2CBundle extends HasTopLevelNetworksBundle{
  23   val outer: HasPeripheryI2C
  24   val i2cs = Vec(outer.i2cParams.size, new I2CPort)
  25 }
  26
  27 trait HasPeripheryI2CModule extends HasTopLevelNetworksModule {
  28   val outer: HasPeripheryI2C
  29   val io: HasPeripheryI2CBundle
  30   (io.i2cs zip outer.i2c).foreach { case (io, device) =>
  31     io <> device.module.io.port
  32   }
  33 }