6bf40aedd5526975ebfd5fe7ecb186b643927c09
[sifive-blocks.git] / src / main / scala / devices / i2c / I2CPins.scala
1 // See LICENSE for license details.
2 package sifive.blocks.devices.i2c
3
4 import Chisel._
5 import chisel3.experimental.{withClockAndReset}
6 import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
7 import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
8
9 class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
10
11 val scl: T = pingen()
12 val sda: T = pingen()
13
14 override def cloneType: this.type =
15 this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
16
17 def fromPort(i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = {
18 withClockAndReset(clock, reset) {
19 scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
20 scl.o.oe := i2c.scl.oe
21 i2c.scl.in := SyncResetSynchronizerShiftReg(scl.i.ival, syncStages, init = Bool(true),
22 name = Some("i2c_scl_sync"))
23
24 sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B)
25 sda.o.oe := i2c.sda.oe
26 i2c.sda.in := SyncResetSynchronizerShiftReg(sda.i.ival, syncStages, init = Bool(true),
27 name = Some("i2c_sda_sync"))
28 }
29 }
30 }