src/main/scala/devices/mockaon/MockAON.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.mockaon
   3
   4 import Chisel._
   5 import chisel3.experimental.MultiIOModule
   6 import freechips.rocketchip.config.Parameters
   7 import freechips.rocketchip.regmapper._
   8 import freechips.rocketchip.tilelink._
   9
  10 import sifive.blocks.util.GenericTimer
  11
  12 case class MockAONParams(
  13     address: BigInt = BigInt(0x10000000),
  14     nBackupRegs: Int = 16) {
  15   def size: Int = 0x1000
  16   def regBytes: Int = 4
  17   def wdogOffset: Int = 0
  18   def rtcOffset: Int = 0x40
  19   def backupRegOffset: Int = 0x80
  20   def pmuOffset: Int = 0x100
  21 }
  22
  23 class MockAONPMUIO extends Bundle {
  24   val vddpaden = Bool(OUTPUT)
  25   val dwakeup = Bool(INPUT)
  26 }
  27
  28 class MockAONMOffRstIO extends Bundle {
  29   val hfclkrst = Bool(OUTPUT)
  30   val corerst = Bool(OUTPUT)
  31 }
  32
  33 trait HasMockAONBundleContents extends Bundle {
  34
  35   // Output of the Power Management Sequencer
  36   val moff = new MockAONMOffRstIO
  37
  38   // This goes out to wrapper
  39   // to be combined to create aon_rst.
  40   val wdog_rst = Bool(OUTPUT)
  41
  42   // This goes out to wrapper
  43   // and comes back as our clk
  44   val lfclk = Clock(OUTPUT)
  45
  46   val pmu = new MockAONPMUIO
  47
  48   val lfextclk = Clock(INPUT)
  49
  50   val resetCauses = new ResetCauses().asInput
  51 }
  52
  53 trait HasMockAONModuleContents extends MultiIOModule with HasRegMap {
  54   val io: HasMockAONBundleContents
  55   val params: MockAONParams
  56   val c = params
  57
  58   // the expectation here is that Chisel's implicit reset is aonrst,
  59   // which is asynchronous, so don't use synchronous-reset registers.
  60
  61   val rtc = Module(new RTC)
  62
  63   val pmu = Module(new PMU(new DevKitPMUConfig))
  64   io.moff <> pmu.io.control
  65   io.pmu.vddpaden := pmu.io.control.vddpaden
  66   pmu.io.wakeup.dwakeup := io.pmu.dwakeup
  67   pmu.io.wakeup.awakeup := Bool(false)
  68   pmu.io.wakeup.rtc := rtc.io.ip(0)
  69   pmu.io.resetCauses := io.resetCauses
  70   val pmuRegMap = {
  71     val regs = pmu.io.regs.wakeupProgram ++ pmu.io.regs.sleepProgram ++
  72       Seq(pmu.io.regs.ie, pmu.io.regs.cause, pmu.io.regs.sleep, pmu.io.regs.key)
  73     for ((r, i) <- regs.zipWithIndex)
  74       yield (c.pmuOffset + c.regBytes*i) -> Seq(r.toRegField())
  75   }
  76   interrupts(1) := rtc.io.ip(0)
  77
  78   val wdog = Module(new WatchdogTimer)
  79   io.wdog_rst := wdog.io.rst
  80   wdog.io.corerst := pmu.io.control.corerst
  81   interrupts(0) := wdog.io.ip(0)
  82
  83   // If there are multiple lfclks to choose from, we can mux them here.
  84   io.lfclk := io.lfextclk
  85
  86   val backupRegs = Seq.fill(c.nBackupRegs)(Reg(UInt(width = c.regBytes * 8)))
  87   val backupRegMap =
  88     for ((reg, i) <- backupRegs.zipWithIndex)
  89       yield (c.backupRegOffset + c.regBytes*i) -> Seq(RegField(reg.getWidth, RegReadFn(reg), RegWriteFn(reg)))
  90
  91   regmap((backupRegMap ++
  92     GenericTimer.timerRegMap(wdog, c.wdogOffset, c.regBytes) ++
  93     GenericTimer.timerRegMap(rtc, c.rtcOffset, c.regBytes) ++
  94     pmuRegMap):_*)
  95
  96 }
  97
  98 class TLMockAON(w: Int, c: MockAONParams)(implicit p: Parameters)
  99   extends TLRegisterRouter(c.address, "aon", Seq("sifive,aon0"), interrupts = 2, size = c.size, beatBytes = w, concurrency = 1)(
 100   new TLRegBundle(c, _)    with HasMockAONBundleContents)(
 101   new TLRegModule(c, _, _) with HasMockAONModuleContents)