src/main/scala/devices/mockaon/MockAONPeriphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.mockaon
   3
   4 import Chisel._
   5 import freechips.rocketchip.config.Field
   6 import freechips.rocketchip.util.SynchronizerShiftReg
   7 import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
   8 import freechips.rocketchip.devices.debug.HasPeripheryDebug
   9 import freechips.rocketchip.devices.tilelink.HasPeripheryClint
  10 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
  11 import freechips.rocketchip.tilelink.{TLAsyncCrossingSource}
  12 import freechips.rocketchip.interrupts._
  13 import freechips.rocketchip.util.ResetCatchAndSync
  14
  15 case object PeripheryMockAONKey extends Field[MockAONParams]
  16
  17 trait HasPeripheryMockAON extends HasPeripheryBus
  18     with HasInterruptBus
  19     with HasPeripheryClint
  20     with HasPeripheryDebug {
  21   // We override the clock & Reset here so that all synchronizers, etc
  22   // are in the proper clock domain.
  23   val mockAONParams= p(PeripheryMockAONKey)
  24   val aon = LazyModule(new MockAONWrapper(pbus.beatBytes, mockAONParams))
  25   aon.node := pbus.toAsyncVariableWidthSlaves(sync = 3)
  26   ibus.fromAsync := aon.intnode
  27 }
  28
  29 trait HasPeripheryMockAONBundle {
  30   val aon: MockAONWrapperBundle
  31   def coreResetCatchAndSync(core_clock: Clock) = {
  32     ResetCatchAndSync(core_clock, aon.rsts.corerst, 20)
  33   }
  34 }
  35
  36 trait HasPeripheryMockAONModuleImp extends LazyModuleImp with HasPeripheryMockAONBundle {
  37   val outer: HasPeripheryMockAON
  38   val aon = IO(new MockAONWrapperBundle)
  39
  40   aon <> outer.aon.module.io
  41
  42   // Explicit clock & reset are unused in MockAONWrapper.
  43   // Tie  to check this assumption.
  44   outer.aon.module.clock := Bool(false).asClock
  45   outer.aon.module.reset := Bool(true)
  46
  47   // Synchronize the external toggle into the clint
  48   val rtc_sync = SynchronizerShiftReg(outer.aon.module.io.rtc.asUInt.toBool, 3, Some("rtc"))
  49   val rtc_last = Reg(init = Bool(false), next=rtc_sync)
  50   val rtc_tick = Reg(init = Bool(false), next=(rtc_sync & (~rtc_last)))
  51
  52   outer.clint.module.io.rtcTick := rtc_tick
  53
  54   outer.aon.module.io.ndreset := outer.debug.module.io.ctrl.ndreset
  55 }