src/main/scala/devices/pwm/PWMPeriphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.pwm
   3
   4 import Chisel._
   5 import freechips.rocketchip.config.Field
   6 import freechips.rocketchip.subsystem.BaseSubsystem
   7 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
   8 import freechips.rocketchip.util.HeterogeneousBag
   9 import sifive.blocks.devices.pinctrl.{Pin}
  10
  11 class PWMPortIO(val c: PWMParams) extends Bundle {
  12   val port = Vec(c.ncmp, Bool()).asOutput
  13   override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
  14 }
  15
  16
  17 case object PeripheryPWMKey extends Field[Seq[PWMParams]]
  18
  19 trait HasPeripheryPWM { this: BaseSubsystem =>
  20   val pwmParams = p(PeripheryPWMKey)
  21   val pwms = pwmParams.zipWithIndex.map { case(params, i) =>
  22     val name = Some(s"pwm_$i")
  23     val pwm = LazyModule(new TLPWM(pbus.beatBytes, params)).suggestName(name)
  24     pbus.toVariableWidthSlave(name) { pwm.node }
  25     ibus.fromSync := pwm.intnode
  26     pwm
  27   }
  28 }
  29
  30 trait HasPeripheryPWMBundle {
  31   val pwm: HeterogeneousBag[PWMPortIO]
  32
  33 }
  34
  35 trait HasPeripheryPWMModuleImp extends LazyModuleImp with HasPeripheryPWMBundle {
  36   val outer: HasPeripheryPWM
  37   val pwm = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
  38
  39   (pwm zip outer.pwms) foreach { case (io, device) =>
  40     io.port := device.module.io.gpio
  41   }
  42 }