src/main/scala/devices/pwm/PWMPeriphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.pwm
   3
   4 import Chisel._
   5 import freechips.rocketchip.config.Field
   6 import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
   7 import freechips.rocketchip.chip.HasSystemNetworks
   8 import freechips.rocketchip.tilelink.TLFragmenter
   9 import freechips.rocketchip.util.HeterogeneousBag
  10
  11 import sifive.blocks.devices.gpio._
  12
  13 class PWMPortIO(val c: PWMParams) extends Bundle {
  14   val port = Vec(c.ncmp, Bool()).asOutput
  15   override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
  16 }
  17
  18 class PWMPinsIO(val c: PWMParams) extends Bundle {
  19   val pwm = Vec(c.ncmp, new GPIOPin)
  20 }
  21
  22 class PWMGPIOPort(val c: PWMParams) extends Module {
  23   val io = new Bundle {
  24     val pwm = new PWMPortIO(c).flip()
  25     val pins = new PWMPinsIO(c)
  26   }
  27
  28   GPIOOutputPinCtrl(io.pins.pwm, io.pwm.port.asUInt)
  29 }
  30
  31 case object PeripheryPWMKey extends Field[Seq[PWMParams]]
  32
  33 trait HasPeripheryPWM extends HasSystemNetworks {
  34   val pwmParams = p(PeripheryPWMKey)
  35   val pwms = pwmParams map { params =>
  36     val pwm = LazyModule(new TLPWM(peripheryBusBytes, params))
  37     pwm.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
  38     intBus.intnode := pwm.intnode
  39     pwm
  40   }
  41 }
  42
  43 trait HasPeripheryPWMBundle {
  44   val pwms: HeterogeneousBag[PWMPortIO]
  45
  46   def PWMtoGPIOPins(dummy: Int = 1): Seq[PWMPinsIO] = pwms.map { p =>
  47     val pins = Module(new PWMGPIOPort(p.c))
  48     pins.io.pwm <> p
  49     pins.io.pins
  50   }
  51 }
  52
  53 trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp with HasPeripheryPWMBundle {
  54   val outer: HasPeripheryPWM
  55   val pwms = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
  56
  57   (pwms zip outer.pwms) foreach { case (io, device) =>
  58     io.port := device.module.io.gpio
  59   }
  60 }