src/main/scala/devices/spi/SPIPeriphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.spi
   3
   4 import Chisel._
   5 import freechips.rocketchip.config.Field
   6 import freechips.rocketchip.subsystem.BaseSubsystem
   7 import freechips.rocketchip.diplomacy.{LazyModule,LazyModuleImp,BufferParams}
   8 import freechips.rocketchip.tilelink.{TLFragmenter,TLBuffer}
   9 import freechips.rocketchip.util.HeterogeneousBag
  10
  11 case object PeripherySPIKey extends Field[Seq[SPIParams]]
  12
  13 trait HasPeripherySPI { this: BaseSubsystem =>
  14   val spiParams = p(PeripherySPIKey)
  15   val spis = spiParams.zipWithIndex.map { case(params, i) =>
  16     val name = Some(s"spi_$i")
  17     val spi = LazyModule(new TLSPI(pbus.beatBytes, params)).suggestName(name)
  18     pbus.toVariableWidthSlave(name) { spi.rnode }
  19     ibus.fromSync := spi.intnode
  20     spi
  21   }
  22 }
  23
  24 trait HasPeripherySPIBundle {
  25   val spi: HeterogeneousBag[SPIPortIO]
  26
  27 }
  28
  29 trait HasPeripherySPIModuleImp extends LazyModuleImp with HasPeripherySPIBundle {
  30   val outer: HasPeripherySPI
  31   val spi = IO(HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_))))
  32
  33   (spi zip outer.spis).foreach { case (io, device) =>
  34     io <> device.module.io.port
  35   }
  36 }
  37
  38 case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]]
  39
  40 trait HasPeripherySPIFlash { this: BaseSubsystem =>
  41   val spiFlashParams = p(PeripherySPIFlashKey)
  42   val qspis = spiFlashParams.zipWithIndex.map { case(params, i) =>
  43     val name = Some(s"qspi_$i")
  44     val qspi = LazyModule(new TLSPIFlash(pbus.beatBytes, params))
  45     pbus.toVariableWidthSlave(name) { qspi.rnode }
  46     qspi.fnode := pbus.toFixedWidthSlave(name) {
  47       TLFragmenter(1, pbus.blockBytes) :=
  48         TLBuffer(BufferParams(params.fBufferDepth), BufferParams.none)
  49     }
  50     ibus.fromSync := qspi.intnode
  51     qspi
  52   }
  53 }
  54
  55 trait HasPeripherySPIFlashBundle {
  56   val qspi: HeterogeneousBag[SPIPortIO]
  57
  58 }
  59
  60 trait HasPeripherySPIFlashModuleImp extends LazyModuleImp with HasPeripherySPIFlashBundle {
  61   val outer: HasPeripherySPIFlash
  62   val qspi = IO(HeterogeneousBag(outer.spiFlashParams.map(new SPIPortIO(_))))
  63
  64   (qspi zip outer.qspis) foreach { case (io, device) =>
  65     io <> device.module.io.port
  66   }
  67 }